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Commit a1e81d0d authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Changes to PTS UG

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doc/pts/Makefile
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FILE=pts_hdlguide
all:
pdflatex -synctex=1 -interaction=nonstopmode *.tex
bibtex *.aux
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
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doc/pts/cern-title.tex 0 → 100644
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\begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{ \LARGE \textbf{CONV-TTL-BLO PTS HDL Guide}}
\noindent \rule{\textwidth}{.1cm}
\hfill\today
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
doc/pts/pts_hdlguide.bib
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......@@ -26,3 +26,18 @@
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
@misc{ctb-ug,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO User Guide}},
day = 25,
month = 06,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/263}}
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
doc/pts/pts_hdlguide.pdf
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doc/pts/pts_hdlguide.tex
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%==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{color}
\usepackage[toc,page]{appendix}
% Header and footer customization
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
\title{
\textbf{
Conv-TTL-Blo Production Test Suite\\
HDL Developer's Guide\\}}
\author{Theodor-Adrian Stana\\
% \href{mailto:t.stana@cern.ch}{\textbf{\textit{t.stana@cern.ch}}}\\
BE-CO-HT\\
}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{fig/cern-logo.png}
\end{center}
\end{figure}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\section*{Revision history}
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
03-05-2013 & 0.1 & First draft \\
27-06-2013 & 0.2 & Changed title page, layout, and updated info \\
\hline
\end{tabular}
}
\maketitle{}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
\pagebreak
%------------------------------------------------------------------------------
% List of figs, tables, abbrevs
%------------------------------------------------------------------------------
\pagebreak
\listoffigures
\listoftables
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\thispagestyle{empty}
\section*{List of abbreviations}
\section*{List of Abbreviations}
\begin{tabular}{l l}
\textit{DAC} & Digital-to-Analog Converter \\
\textit{FPGA} & Field-Programmable Gate Array \\
\textit{HDL} & High-level Description Language \\
\textit{PTS} & Production Test Suite \\
\textit{RTM} & Rear-Transition Module \\
\textit{PLL} & Phase-Locked Loop \\
\textit{SFP} & Small Form-factor Pluggable (in the context of SFP connectors) \\
\textit{SPI} & Serial Peripheral Interface \\
FPGA & Field-Programmable Gate Array \\
PTS & Production Test Suite \\
SysMon & (ELMA) System Monitor \\
\end{tabular}
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
%======================================================================================
% SEC: Intro
%======================================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
This document presents a high-level view of the firmware implemented on the FPGA for the
Production Test Suite (PTS) project for the Conv-TTL-Blo board. The document starts by
presenting the memory map, followed by sections describing the logic implemented to run
the tests comprising PTS. Then, the folder structure is described, along with hints on where
the developer should look for specific files. This is followed by a presentation on the
structure of the top-level HDL together with hints on where the developer should look in case
changes are to be made to the code.
Production Test Suite (PTS) project for the Conv-TTL-Blo board. More involved details can
be found by consulting the PTS HDL, which can be obtained by cloning the OHWR git repository
for the Conv-TTL-Blo PTS project \textcolor{red}{REFERENCE}.
All the logic implemented on the FPGA is written in VHDL and can be obtained freely by cloning
the OHWR git repository for the Conv-TTL-Blo PTS project at the following link:
\textcolor{red}{REFERENCE THE OTHER DOCUMENTS}
\textcolor{red}{link ohwr repo}
%======================================================================================
% SEC: Memory map
%======================================================================================
\section{PTS system}
\label{sec:pts-sys}
\textcolor{red}{REFERENCE THE OTHER DOCUMENTS}
The PTS system is contained within a rack containing an ELMA crate, the laptop with the
PTS software installed on it and all other accessories necessary for running tests. More
information about the PTS system can be found in \textcolor{red}{REFER USER GUIDE}.
The ELMA crate within the PTS contains a system monitor (SysMon) board that monitors
voltage levels, temperatures and controls fan speeds for the crate fans. The crate
can be accessed via SNMP to send commands to the VME boards inside the crate.
This is relevant in the case of the PTS system in that the CONV-TTL-BLO board can be
accessed through the serial (I$^2$C) interface on the VME P1 connector. The PTS software on the
PTS laptop connects to the crate through \textit{telnet} and sends \textit{readreg} and
\textit{writereg} commands to the crate; the commands are translated by the SysMon to
I$^2$C transfers to the CONV-TTL-BLO. More information about this can be found in
\cite{ctb-ug} and \cite{sysmon-ug}.
%======================================================================================
% SEC: Memory map
%======================================================================================
\pagebreak
\section{Memory Map}
\section{Memory map}
\label{sec:memmap}
Various peripherals on the Conv-TTL-Blo board can be accessed by sending telnet commands
to the VME crate; these commands are sent to the converter board by means of the serial
I$2$C interface on the VME P1 connector. Each board peripheral is accessible via a
memory-mapped Wishbone interface. A \textit{vme64x\_i2c} component
\textcolor{red}{(reference)} is used alongside a Wishbone crossbar component
\textcolor{red}{(reference)} to translate the I$2$C transfers into Wishbone
Each board peripheral is accessible via a memory-mapped Wishbone interface. A
\textit{vme64x\_i2c} component \textcolor{red}{(reference)} is used alongside a Wishbone
crossbar component \textcolor{red}{(reference)} to translate the I$2$C transfers into Wishbone
transfers. Fig.~\ref{fig:memmapping} shows how these two components are connected to various
other memory-mapped Wishbone slaves.
......
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