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Conv TTL Blocking
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Conv TTL Blocking
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a8566fda
Commit
a8566fda
authored
Nov 22, 2012
by
Carlos Gil Soriano
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Kickstart for the image integrating everything
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4 changed files
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1102 additions
and
758 deletions
+1102
-758
FPGAbank.ucf
hdl/IMAGES/image1/constraints/FPGAbank.ucf
+352
-342
image1.xise
hdl/IMAGES/image1/project/image1.xise
+470
-0
image1_pkg.vhd
hdl/IMAGES/image1/rtl/image1_pkg.vhd
+115
-0
image1_top.vhd
hdl/IMAGES/image1/rtl/image1_top.vhd
+165
-416
No files found.
hdl/IMAGES/image1/constraints/FPGAbank.ucf
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a8566fda
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hdl/IMAGES/image1/project/image1.xise
0 → 100644
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a8566fda
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hdl/IMAGES/image1/rtl/image1_pkg.vhd
0 → 100644
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a8566fda
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
IEEE
.
NUMERIC_STD
.
ALL
;
package
image1_pkg
is
component
basic_trigger_top
generic
(
g_NUMBER_OF_CHANNELS
:
NATURAL
:
=
6
);
port
(
FPGA_CLK_P
:
in
STD_LOGIC
;
FPGA_CLK_N
:
in
STD_LOGIC
;
led_pw_o
:
out
STD_LOGIC
;
led_err_o
:
out
STD_LOGIC
;
led_ttl_o
:
out
STD_LOGIC
;
fpga_o_en
:
out
STD_LOGIC
;
fpga_o_ttl_en
:
out
STD_LOGIC
;
fpga_o_inv_en
:
out
STD_LOGIC
;
fpga_o_blo_en
:
out
STD_LOGIC
;
level
:
in
STD_LOGIC
;
switch_i
:
in
STD_LOGIC
;
--! General enable
manual_rst_n_o
:
out
STD_LOGIC
;
--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front
:
in
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
pulse_o_front
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
pulse_i_rear
:
in
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
pulse_o_rear
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
led_o_front
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
led_o_rear
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
--! This LED will show the status of the PLL
led_link_up_o
:
out
STD_LOGIC
;
--! WR LEDs not to let them ON
led_pps_o
:
out
STD_LOGIC
;
led_wr_ok_o
:
out
STD_LOGIC
;
inv_i
:
in
STD_LOGIC_VECTOR
(
4
downto
1
);
inv_o
:
out
STD_LOGIC_VECTOR
(
4
downto
1
));
end
component
;
component
i2c_slave_top
generic
(
g_WB_CLK_PERIOD
:
TIME
:
=
c_WB_CLK_PERIOD
);
-- Specify in ns
port
(
sda_oen
:
out
STD_LOGIC
;
sda_i
:
in
STD_LOGIC
;
sda_o
:
out
STD_LOGIC
;
scl_oen
:
out
STD_LOGIC
;
scl_i
:
in
STD_LOGIC
;
scl_o
:
out
STD_LOGIC
;
wb_clk
:
in
STD_LOGIC
;
wb_rst_i
:
in
STD_LOGIC
;
wb_master_stb_o
:
out
STD_LOGIC
;
wb_master_cyc_o
:
out
STD_LOGIC
;
wb_master_sel_o
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
wb_master_we_o
:
out
STD_LOGIC
;
wb_master_data_i
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
wb_master_data_o
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
wb_master_addr_o
:
out
STD_LOGIC_VECTOR
(
15
downto
0
);
wb_master_ack_i
:
in
STD_LOGIC
;
wb_master_rty_i
:
in
STD_LOGIC
;
wb_master_err_i
:
in
STD_LOGIC
;
wb_slave_stb_i
:
in
STD_LOGIC
;
wb_slave_cyc_i
:
in
STD_LOGIC
;
wb_slave_sel_i
:
in
STD_LOGIC_VECTOR
(
3
downto
0
);
wb_slave_we_i
:
in
STD_LOGIC
;
wb_slave_data_i
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
wb_slave_data_o
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
wb_slave_addr_i
:
in
STD_LOGIC_VECTOR
(
3
downto
0
);
wb_slave_ack_o
:
out
STD_LOGIC
;
wb_slave_rty_o
:
out
STD_LOGIC
;
wb_slave_err_o
:
out
STD_LOGIC
;
pf_wb_addr_o
:
out
STD_LOGIC
;
rd_done_o
:
out
STD_LOGIC
;
wr_done_o
:
out
STD_LOGIC
;
i2c_addr_i
:
in
STD_LOGIC_VECTOR
(
6
downto
0
));
end
component
;
component
m25p32_top
generic
(
g_WB_ADDR_LENGTH
:
NATURAL
:
=
c_WORDS_PER_PAGE_BITS
+
1
);
port
(
wb_rst_i
:
in
STD_LOGIC
;
wb_clk
:
in
STD_LOGIC
;
wb_we_i
:
in
STD_LOGIC
;
wb_stb_i
:
in
STD_LOGIC
;
wb_cyc_i
:
in
STD_LOGIC
;
wb_sel_i
:
in
STD_LOGIC_VECTOR
(
3
downto
0
);
wb_data_i
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
wb_data_o
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
wb_addr_i
:
in
STD_LOGIC_VECTOR
(
g_WB_ADDR_LENGTH
-
1
downto
0
);
wb_ack_o
:
out
STD_LOGIC
;
wb_rty_o
:
out
STD_LOGIC
;
wb_err_o
:
out
STD_LOGIC
;
miso_word_rcv
:
out
STD_LOGIC
;
op_finished_o
:
out
STD_LOGIC
;
prom_mosi_o
:
out
STD_LOGIC
;
prom_cclk_o
:
out
STD_LOGIC
;
prom_cs0_b_n_o
:
out
STD_LOGIC
;
prom_din_i
:
in
STD_LOGIC
);
end
component
;
end
image1_pkg
;
package
body
image1_pkg
is
end
image1_pkg
;
hdl/IMAGES/image1/rtl/image1_top.vhd
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a8566fda
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