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ab2910f4
Commit
ab2910f4
authored
Oct 25, 2012
by
Carlos Gil Soriano
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parent
23ca8a8f
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6 changed files
with
195 additions
and
65 deletions
+195
-65
ctdah_pkg.vhd
hdl/ctdah_lib/rtl/ctdah_pkg.vhd
+11
-0
m25p32_pkg.vhd
hdl/m25p32/rtl/m25p32_pkg.vhd
+45
-1
m25p32_top_tb.vhd
hdl/m25p32/test/m25p32_top_tb.vhd
+126
-53
m25p32_top_tb_pkg.vhd
hdl/m25p32/test/m25p32_top_tb_pkg.vhd
+2
-0
spi_master_core.vhd
hdl/spi_master_multifield/rtl/spi_master_core.vhd
+3
-3
spi_master_regs.vhd
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
+8
-8
No files found.
hdl/ctdah_lib/rtl/ctdah_pkg.vhd
View file @
ab2910f4
...
...
@@ -66,6 +66,17 @@ package ctdah_pkg is
output
:
out
STD_LOGIC
);
end
component
;
component
gc_simple_monostable
is
generic
(
g_PULSE_LENGTH
:
NATURAL
:
=
20
);
port
(
rst
:
in
STD_LOGIC
;
clk
:
in
STD_LOGIC
;
input
:
in
STD_LOGIC
;
output
:
out
STD_LOGIC
;
output_n
:
out
STD_LOGIC
);
end
component
;
component
gc_RAM
is
generic
(
g_DATA_WIDTH
:
INTEGER
:
=
32
;
g_ADDR_WIDTH
:
INTEGER
:
=
8
);
...
...
hdl/m25p32/rtl/m25p32_pkg.vhd
View file @
ab2910f4
...
...
@@ -264,6 +264,17 @@ package m25p32_pkg is
constant
c_SE_inst
:
STD_LOGIC_VECTOR
(
7
downto
0
)
:
=
X"D8"
;
constant
c_BE_inst
:
STD_LOGIC_VECTOR
(
7
downto
0
)
:
=
X"C7"
;
type
t_spi_instruction
is
(
WREN
,
WRDI
,
RDID
,
RDSR
,
WRSR
,
READ
,
PP
,
SE
,
BE
,
NULL_INST
);
constant
c_SPI0_IDLE
:
r_SPI0
:
=
(
CPOL
=>
c_SPI_CFG
.
CPOL
,
CPHA
=>
c_SPI_CFG
.
CPHA
,
BREAD
=>
(
others
=>
'0'
),
...
...
@@ -519,7 +530,9 @@ package m25p32_pkg is
return
r_word
;
function
f_page
(
signal
page
:
in
STD_LOGIC_VECTOR
(
c_PAGE_SIZE
*
8
-1
downto
0
))
return
r_page
;
function
f_spi_instruction
(
signal
spi_inst_slv
:
STD_LOGIC_VECTOR
(
7
downto
0
))
return
t_spi_instruction
;
end
m25p32_pkg
;
...
...
@@ -721,4 +734,35 @@ package body m25p32_pkg is
return
v_page
;
end
function
f_page
;
function
f_spi_instruction
(
signal
spi_inst_slv
:
STD_LOGIC_VECTOR
(
7
downto
0
))
return
t_spi_instruction
is
variable
v_return
:
t_spi_instruction
;
begin
case
spi_inst_slv
is
when
c_WREN_inst
=>
v_return
:
=
WREN
;
when
c_WRDI_inst
=>
v_return
:
=
WRDI
;
when
c_RDID_inst
=>
v_return
:
=
RDID
;
when
c_RDSR_inst
=>
v_return
:
=
RDSR
;
when
c_WRSR_inst
=>
v_return
:
=
WRSR
;
when
c_READ_inst
=>
v_return
:
=
READ
;
when
c_PP_inst
=>
v_return
:
=
PP
;
when
c_SE_inst
=>
v_return
:
=
SE
;
when
c_BE_inst
=>
v_return
:
=
BE
;
when
others
=>
v_return
:
=
NULL_INST
;
end
case
;
return
v_return
;
end
function
f_spi_instruction
;
end
m25p32_pkg
;
hdl/m25p32/test/m25p32_top_tb.vhd
View file @
ab2910f4
This diff is collapsed.
Click to expand it.
hdl/m25p32/test/m25p32_top_tb_pkg.vhd
View file @
ab2910f4
...
...
@@ -56,6 +56,7 @@ package m25p32_top_tb_pkg is
wb_rty_o
:
out
STD_LOGIC
;
wb_err_o
:
out
STD_LOGIC
;
miso_word_rcv
:
out
STD_LOGIC
;
op_finished_o
:
out
STD_LOGIC
;
prom_mosi_o
:
out
STD_LOGIC
;
...
...
@@ -167,6 +168,7 @@ package body m25p32_top_tb_pkg is
wb_sel
<=
X"F"
;
wb_addr
<=
reg_addr
;
wait
until
rising_edge
(
wb_clk
);
wait
until
wb_data
'event
;
--! Here we wait for the ack and keep till operation is finished
read_data
<=
wb_data
;
wait
until
rising_edge
(
wb_clk
);
...
...
hdl/spi_master_multifield/rtl/spi_master_core.vhd
View file @
ab2910f4
...
...
@@ -603,7 +603,7 @@ begin
s_SPI2
.
SENT_ADDR
<=
'1'
;
when
S4_DATA
=>
s_SPI2
.
SENT_DATA
<=
'1'
;
when
S5
_READ
=>
when
S5
U_READ
=>
s_SPI2
.
READ_DONE
<=
'1'
;
when
others
=>
null
;
...
...
@@ -807,12 +807,12 @@ begin
s_spi_miso_data
<=
(
others
=>
'0'
);
else
if
rising_edge
(
s_read_edge_counter_clk
)
then
else
s_spi_miso_data
<=
(
others
=>
'0'
);
if
s_spi_clk_fsm_d0
=
S5_READ
then
s_spi_miso_data
<=
s_spi_miso_data
(
30
downto
0
)
&
spi_miso_i
;
end
if
;
else
end
if
;
end
if
;
end
process
p_miso
;
...
...
@@ -830,7 +830,7 @@ begin
s_rd_SPI3
<=
'1'
;
end
if
;
end
if
;
end
process
p_rd_miso
;
end
process
p_
comb_
rd_miso
;
-----------------------------------------------------------
--! fsm to determine access to SPI lines
...
...
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
View file @
ab2910f4
...
...
@@ -90,17 +90,17 @@ begin
begin
if
rising_edge
(
wb_clk_i
)
then
if
wb_rst_i
=
'1'
then
s_SPI0
<=
f_STD_LOGIC_VECTOR
(
c_SPI0_default
);
s_SPI1
<=
f_STD_LOGIC_VECTOR
(
c_SPI1_default
);
s_wb_ack
<=
'0'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
s_SPI0
<=
f_STD_LOGIC_VECTOR
(
c_SPI0_default
);
s_SPI1
<=
f_STD_LOGIC_VECTOR
(
c_SPI1_default
);
elsif
(
wb_stb_i
=
'1'
and
wb_cyc_i
=
'1'
)
then
s_wb_ack
<=
'0'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
if
(
s_wb_ack
or
s_wb_rty
or
s_wb_err
)
=
'1'
then
s_wb_ack
<=
'0'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
else
s_wb_ack
<=
'0'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
case
wb_we_i
is
when
'1'
=>
case
wb_addr_i
is
...
...
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