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Conv TTL Blocking
Commit abe238c9 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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image1 testbench assembled. Ready to be debugged the whole firmware.

parent a81703d3
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hdl/IMAGES/image1/project/image1.gise
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hdl/IMAGES/image1/project/image1.xise
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hdl/IMAGES/image1/project/waveform/wave.do 0 → 100644
View file @ abe238c9
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /image1_top_tb/uut/s_clk
add wave -noupdate /image1_top_tb/uut/s_rst
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_link_up_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_pps_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_wr_ok_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_pw_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_err_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_ttl_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_pulse_led
add wave -noupdate -group {Front Panel} /image1_top_tb/s_pulse_i
add wave -noupdate -group {Front Panel} /image1_top_tb/s_pulse_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_inv_i
add wave -noupdate -group {Front Panel} /image1_top_tb/s_inv_o
add wave -noupdate -group I2C /image1_top_tb/s_sda_slave_oen
add wave -noupdate -group I2C /image1_top_tb/s_scl_slave_oen
add wave -noupdate -group I2C /image1_top_tb/s_I2C_slave_i
add wave -noupdate -group I2C /image1_top_tb/s_I2C_slave_o
add wave -noupdate -group I2C /image1_top_tb/s_FPGA_GA
add wave -noupdate -group I2C /image1_top_tb/s_FPGA_GAP
add wave -noupdate -group SPI /image1_top_tb/s_SPI_master_i
add wave -noupdate -group SPI /image1_top_tb/s_SPI_master_o
add wave -noupdate -group CTRL /image1_top_tb/s_fpga_en
add wave -noupdate -group CTRL /image1_top_tb/level
add wave -noupdate -group CTRL /image1_top_tb/switch_i
add wave -noupdate -group CTRL /image1_top_tb/s_RTM_id_i
add wave -noupdate -group CTRL /image1_top_tb/manual_rst_n_o
add wave -noupdate /image1_top_tb/s_i2c_addr_op
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {672660935 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {998063239 ps} {1000101935 ps}
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ abe238c9
......@@ -3,6 +3,7 @@ library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
--! Packages from IP cores
use work.wishbone_pkg.ALL;
......@@ -13,8 +14,26 @@ use work.rtm_detector_pkg.ALL;
package image1_pkg is
constant c_WB_CLK_PERIOD : TIME := 50 ns;
constant c_RST_CLKS : NATURAL := 256; --! @8ns
--! Blocking repetition parameters
constant c_NUMBER_OF_CHANNELS : NATURAL := 6;
constant c_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
constant c_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns;
constant c_PLL_IN_PERIOD : TIME := 8 ns;
constant c_CLKIN_PERIOD : REAL := REAL(c_PLL_IN_PERIOD/(1 ns));
constant c_CLKFBOUT_MULT : NATURAL := 8;
constant c_CLKOUTA_DIVIDE : NATURAL := 20;
constant c_CLKOUTB_DIVIDE : NATURAL := 5;
--! As TIME type is derived from INTEGER, please don't let fractional parts
constant c_WB_CLK_PERIOD : TIME := (c_CLKOUTA_DIVIDE*c_PLL_IN_PERIOD)/c_CLKFBOUT_MULT;
constant c_CLKB_PERIOD : TIME := (c_CLKOUTB_DIVIDE*c_PLL_IN_PERIOD)/c_CLKFBOUT_MULT;
constant c_RST_TIME : TIME := 250 ns;
constant c_RST_PLL_CLKS : NATURAL := c_RST_TIME/c_PLL_IN_PERIOD;
constant c_RST_A_CLKS : NATURAL := c_RST_TIME/c_WB_CLK_PERIOD;
constant c_RST_B_CLKS : NATURAL := c_RST_TIME/c_CLKB_PERIOD;
constant c_NUM_MASTERS : NATURAL := 1;
constant c_NUM_SLAVES : NATURAL := 3;
......@@ -44,8 +63,13 @@ package image1_pkg is
c_MASK_I2C_SLAVE);
component basic_trigger_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (clk_125m_i : in STD_LOGIC;
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
port (clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
......@@ -177,7 +201,25 @@ package image1_pkg is
ok_RTMP_o : out STD_LOGIC);
end component;
-- function check_sys_cfg return BOOLEAN;
end image1_pkg;
package body image1_pkg is
-- function check_sys_cfg return BOOLEAN is
-- variable v_real_tmp : REAL;
-- variable v_time_tmp : TIME;
-- variable v_return : BOOLEAN;
-- begin
-- v_real_tmp := c_CLKIN_PERIOD;
-- assert (v_real_tmp = 0.0) report REAL'image(v_real_tmp) severity Failure;
-- v_time_tmp := c_WB_CLK_PERIOD;
-- assert (v_time_tmp = 0 ns) report TIME'image(v_time_tmp) severity Failure;
-- v_time_tmp := c_CLKB_PERIOD;
-- assert (v_time_tmp = 0 ns) report TIME'image(v_time_tmp) severity Failure;
-- return TRUE;
-- end check_sys_cfg;
end image1_pkg;
hdl/IMAGES/image1/rtl/image1_top.vhd
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hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ abe238c9
library IEEE;
library work;
library modelsim_lib;
use modelsim_lib.util.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALl;
use std.textio.ALL;
use work.image1_pkg.ALL;
use work.image1_top_tb_pkg.ALL;
use work.i2c_tb_pkg.ALL;
use work.wishbone_driver_pkg.ALL;
entity image1_top_tb is
end image1_top_tb;
......@@ -15,7 +19,8 @@ architecture behavior of image1_top_tb is
--! ========================================================================
--! Signals for the image1_top module
--! ========================================================================
signal wb_clk : STD_LOGIC := '0';
signal s_FPGA_CLK_P : STD_LOGIC := '1';
signal s_FPGA_CLK_N : STD_LOGIC := '0';
signal s_led_pw_o : STD_LOGIC;
signal s_led_err_o : STD_LOGIC;
signal s_led_ttl_o : STD_LOGIC;
......@@ -43,7 +48,7 @@ architecture behavior of image1_top_tb is
signal s_led_pps_o : STD_LOGIC;
signal s_led_wr_ok_o : STD_LOGIC;
signal s_fpga_en : t_fpga_en;
signal level : STD_LOGIC;
signal level : STD_LOGIC := '1';
signal switch_i : STD_LOGIC;
signal manual_rst_n_o : STD_LOGIC;
signal s_RTM_id_i : t_RTM_id;
......@@ -67,21 +72,35 @@ architecture behavior of image1_top_tb is
signal s_i2c_driver_read : STD_LOGIC := '0';
signal s_i2c_driver_read_done : STD_LOGIC;
signal wb_clk : STD_LOGIC;
signal s_rst : STD_LOGIC;
begin
s_FPGA_GA <= "00001";
s_FPGA_GAP <= '1';
s_I2C_master_i <= s_I2C_slave_o;
s_I2C_slave_i <= s_I2C_master_o;
--! Clock process definitions
wb_clk_process :process
p_FPGA_CLK :process
begin
wb_clk <= '1';
wait for c_WB_CLK_PERIOD/2;
wb_clk <= '0';
wait for c_WB_CLK_PERIOD/2;
s_FPGA_CLK_P <= not(s_FPGA_CLK_P);
s_FPGA_CLK_N <= not(s_FPGA_CLK_N);
wait for c_PLL_IN_PERIOD/2;
end process;
--! @brief Process to bypass internal signals requiered for correct
--! use of i2c_master_driver
p_sig_spy : process is
begin
init_signal_spy("/uut/s_clk.SYS_A", "wb_clk", 1);
init_signal_spy("/uut/s_rst.SYS_A(c_RST_A_CLKS - 1)", "s_rst", 1);
wait;
end process p_sig_spy;
-- Instantiate the Unit Under Test (UUT)
i2c_driver: i2c_master_driver
......@@ -106,9 +125,9 @@ begin
read_done_o => s_i2c_driver_read_done);
uut: image1_top
generic map(g_NUMBER_OF_CHANNELS => c_NUMBER_OF_CHANNELS)
port map(FPGA_CLK_P =>,
FPGA_CLK_N =>,
generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
port map(FPGA_CLK_P => s_FPGA_CLK_P,
FPGA_CLK_N => s_FPGA_CLK_N,
led_pw_o => s_led_pw_o ,
led_err_o => s_led_err_o,
led_ttl_o => s_led_ttl_o,
......@@ -144,23 +163,17 @@ begin
manual_rst_n_o => manual_rst_n_o,
FPGA_RTMM => s_RTM_id_i.RTMM,
FPGA_RTMP => s_RTM_id_i.RTMP);
end component;
--! Stimulus process
p_i2c_tb: process
procedure set_i2c_wb_feedback is
procedure initial_inputs is
begin
s_feedback_wb_bus <= '1';
wait until rising_edge(wb_clk);
end procedure;
procedure unset_i2c_wb_feedback is
begin
s_feedback_wb_bus <= '0';
wait until rising_edge(wb_clk);
s_pulse_i.REAR <= (others => level);
s_pulse_i.FRONT <= (others => level);
s_inv_i <= (others => level);
-- s_I2C_slave_i <= c_I2C_master_out_default;
end procedure;
procedure start_I2C is
......@@ -220,25 +233,22 @@ begin
end procedure;
begin
wb_rst_i <= '1';
wait for c_WB_CLK_PERIOD*10;
wb_rst_i <= '0';
--! First we place a write
set_i2c_wb_feedback;
start_I2C;
--! Try to write into DTX addr position
write_I2C(c_VME_SLOT, X"0002", X"B16B00B5");
wait for c_WB_CLK_PERIOD*25;
--! Then we read from the FPGA
--unset_i2c_wb_feedback;
start_I2C;
--! We read addr 1 (LT) via I2C
--! Then, the core internally prefetchs via wishbone and then
--! write the register into I2C to the master
read_I2C(c_VME_SLOT, X"BAB1", X"B16B00B5");
wait for c_WB_CLK_PERIOD*25;
initial_inputs;
wait until falling_edge(s_rst);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
-- --! First we place a write
-- start_I2C;
-- --! Try to write into DTX addr position
-- write_I2C(s_FPGA_GA, X"0002", X"B16B00B5");
-- wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
--
-- start_I2C;
-- --! We read addr 1 (LT) via I2C
-- --! Then, the core internally prefetchs via wishbone and then
-- --! write the register into I2C to the master
-- read_I2C(s_FPGA_GA, X"BAB1", X"B16B00B5");
-- wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
end process;
end;
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ abe238c9
......@@ -9,11 +9,13 @@ use IEEE.NUMERIC_STD.ALL;
--use work.i2c_slave_pkg.ALL;
--use work.m25p32_pkg.ALL;
--use work.multiboot_pkg.ALL;
--use work.rtm_detector_pkg.ALL;
use work.image1_pkg.ALL;
use work.rtm_detector_pkg.ALL;
package image1_top_pkg is
package image1_top_tb_pkg is
constant c_NUMBER_OF_CHANNELS : NATURAL := 6;
constant c_NUMBER_OF_CHANNELS : NATURAL
:= work.image1_pkg.c_NUMBER_OF_CHANNELS;
component image1_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
......@@ -111,7 +113,20 @@ package image1_top_pkg is
RTMP : STD_LOGIC_VECTOR(2 downto 0);
end record;
end image1_top_pkg;
constant c_fpga_en_default : t_fpga_en := (GEN => '0',
BLO => '0',
TTL => '0',
INV => '0');
package body image1_top_pkg is
end image1_top_pkg;
constant c_I2C_master_out_default : t_I2C_master_out := (SCL => '1',
SDA => '1');
constant c_RTM_id_default : t_RTM_id
:= (RTMM => STD_LOGIC_VECTOR(c_RTMM_V1),
RTMP =>
STD_LOGIC_VECTOR(c_RTMP_BLOCKING_V1));
end image1_top_tb_pkg;
package body image1_top_tb_pkg is
end image1_top_tb_pkg;
hdl/basic_trigger/rtl/basic_trigger_core.vhd
View file @ abe238c9
---------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 09:58:06 10/12/2011
--
-- Create Date: 09:58:06 10/12/2011
-- Design Name: HDL trigger
-- Module Name: trigger - Behavioral
-- Module Name: trigger - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Tool versions:
-- Description: This is the wishbone trigger which receives a debounced input
-- and outputs a trigger signal for the pulse converter
-- Dependencies: none
--
-- Revision:
-- Revision:
-- Revision 0.1
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
......@@ -24,22 +24,26 @@ use IEEE.NUMERIC_STD.ALL;
use work.ctdah_pkg.ALL;
entity basic_trigger_core is
port (
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
generic(g_CLK_PERIOD : TIME;
g_OUTPUT_PULSE_LENGTH : TIME;
g_LED_BLINKING_LENGTH : TIME);
port (wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC;
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
pulse_n_o : out STD_LOGIC;
crop_o : out STD_LOGIC;
crop_o : out STD_LOGIC;
led_o : out STD_LOGIC
);
led_o : out STD_LOGIC);
end basic_trigger_core;
architecture Behavioral of basic_trigger_core is
constant c_PULSE_LENGTH : NATURAL := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
constant c_LED_LENGTH : NATURAL := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
signal s_pulse : STD_LOGIC;
signal s_deglitched_pulse : STD_LOGIC;
......@@ -51,29 +55,28 @@ begin
s_pulse <= pulse_i;
inst_debo: gc_debouncer
generic map( g_LENGTH => 2)
port map(rst => wb_rst_i,
clk => wb_clk_i,
input => s_pulse,
output => s_deglitched_pulse,
glitch_mask => "11");
pulse_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => 195) --! Produce 1us sharp at the output
port map (rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => pulse_o,
output_n => pulse_n_o);
led_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => 10000000) --! 250ms
port map (
rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => led_o);
--output_n not connected
inst_debo: gc_debouncer
generic map( g_LENGTH => 2)
port map(rst => wb_rst_i,
clk => wb_clk_i,
input => s_pulse,
output => s_deglitched_pulse,
glitch_mask => "11");
pulse_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => c_PULSE_LENGTH)
port map (rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => pulse_o,
output_n => pulse_n_o);
led_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => c_LED_LENGTH)
port map (rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => led_o,
output_n => open);
end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ abe238c9
......@@ -28,41 +28,37 @@ use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity basic_trigger_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (
clk_125m_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
port (clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
end basic_trigger_top;
......@@ -76,7 +72,6 @@ architecture Behavioral of basic_trigger_top is
signal s_crop : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1)
:= (others => '0');
signal s_level : STD_LOGIC;
signal s_fpga_o_en : STD_LOGIC;
......@@ -84,25 +79,15 @@ architecture Behavioral of basic_trigger_top is
signal s_fpga_o_inv_en : STD_LOGIC;
signal s_fpga_o_blo_en : STD_LOGIC;
signal s_clk_125m_i : STD_LOGIC;
signal s_clk_125m_prebufg : STD_LOGIC;
signal s_clk_125m : STD_LOGIC;
signal s_clk_200m_prebufg : STD_LOGIC;
signal s_clk_200m : STD_LOGIC;
signal s_clk_fb_prebufg : STD_LOGIC;
signal s_clk_fb : STD_LOGIC;
constant c_RST_CLKS : NATURAL := 256; --! @8ns
signal s_rst : STD_LOGIC_VECTOR(c_RST_CLKS - 1 downto 0)
:= (others => '1');
type delay_array is array (g_NUMBER_OF_CHANNELS downto 1)
of STD_LOGIC_VECTOR(3 downto 0);
signal s_pulse_i_reg : delay_array;
signal s_pulse_i_reg : delay_array;
signal s_locked : STD_LOGIC;
component basic_trigger_core is
generic(g_CLK_PERIOD : TIME := g_CLK_PERIOD;
g_OUTPUT_PULSE_LENGTH : TIME := g_OUTPUT_PULSE_LENGTH;
g_LED_BLINKING_LENGTH : TIME := g_LED_BLINKING_LENGTH);
port (wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
......@@ -150,69 +135,26 @@ begin
--! and a buffer in the output, there's no need
--! of invert here.
s_clk_125m_i <= clk_125m_i;
-- set up the fabric PLL_BASE to drive the BUFPLL
pll_base_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 8, CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.000, CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.010)
port map (
-- Output clocks
CLKFBOUT => s_clk_fb_prebufg,
CLKOUT0 => s_clk_125m_prebufg,
CLKOUT1 => s_clk_200m_prebufg,
CLKOUT2 => open, CLKOUT3 => open,
CLKOUT4 => open, CLKOUT5 => open,
-- Status and control signals
LOCKED => s_locked, RST => s_rst(c_RST_CLKS - 1),
-- Input clock control
CLKFBIN => s_clk_fb,
CLKIN => s_clk_125m_i);
s_clk_125m_bufg : BUFG
port map (O => s_clk_125m, I => s_clk_125m_prebufg);
s_clk_200m_bufg : BUFG
port map (O => s_clk_200m, I => s_clk_200m_prebufg);
s_clk_fb_bufg : BUFG
port map (O => s_clk_fb, I => s_clk_fb_prebufg);
i_repetitors: for i in 1 to g_NUMBER_OF_CHANNELS generate
begin
trigger: basic_trigger_core
port map (
wb_rst_i => s_rst(c_RST_CLKS - 1),
wb_clk_i => s_clk_200m,
wb_rst_i => rst_i,
wb_clk_i => clk_i,
pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i),
pulse_n_o => s_pulse_n_o(i),
crop_o => open,
led_o => s_led(i));
end generate i_repetitors;
p_reset_chain : process(s_clk_125m_i) is
--! @brief Process to lock the enables so to avoid output glitches
--! on the startup.
--! @param clk_i Main clock used in this clock domain.
p_reset_chain : process(clk_i) is
begin
if rising_edge(s_clk_125m_i) then
s_rst(0) <= '0';
for i in 1 to c_RST_CLKS - 1 loop
s_rst(i) <= s_rst(i-1);
end loop;
if s_rst(c_RST_CLKS - 1) = '1' then
if rising_edge(clk_i) then
if rst_i = '1' then
--! First we reset the FPGA general output enable
--! Then we let one clock delay for the rest of signals
manual_rst_n_o <= '0';
......@@ -220,7 +162,6 @@ begin
s_fpga_o_ttl_en <= '0';
s_fpga_o_inv_en <= '0';
s_fpga_o_blo_en <= '0';
else
manual_rst_n_o <= '1';
s_fpga_o_en <= '1';
......@@ -231,5 +172,4 @@ begin
end if;
end process p_reset_chain;
end Behavioral;
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