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Conv TTL Blocking
Commit accb11b0 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Updating image1 blocking and transfer knowledge document

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doc/TransferKnowledge/report.tex
View file @ accb11b0
......@@ -940,9 +940,17 @@
Remote reprogramming is the key to wind up the development of the IP core
chain needed to perform the PTS in the boards.\\
To achieve this, the \textit{i2c\_slave\_wb\_master}, \textit{m25p32} and
\textit{multiboot} cores should be put together and thoroughly tested. It
should be noted that good understanding of Xilinx's ICAP is needed
\cite{UG380}.\\
\textit{multiboot} cores should be put together and thoroughly tested. An
image has been provided and can be found in:
\begin{itemize}
\item \textbf{CONV-TTL-BLO/hdl/IMAGES/image1}
\end{itemize}
It should be noted that \textit{image1\_core.vhd} has been splitted from
\textit{image1\_top.vhd} to allow \textit{image1\_core.vhd} be reused in
RS485.\\
Most of the work to be done in the VHDL will be testing that a new raw
bitstream has been loaded into the FPGA. It should be noted that good
understanding of Xilinx's ICAP is needed \cite{UG380}.\\
\item \textbf{PTS}\\
After having a stable bitstream with the basic repetition plus the IP
core chain indicated above, PTS will be "easilly" carried out. That will
......
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ accb11b0
......@@ -8,23 +8,14 @@
NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_SYSRESET_N" LOC = L20;
NET "FPGA_SYSRESET_N" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = "LVCMOS33";
NET "CLK20_VCXO" LOC = E16;
NET "CLK20_VCXO" IOSTANDARD = "LVCMOS33";
NET "CLK20_VCXO" TNM_NET = "CLK20_VCXO";
TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
NET "FPGA_CLK_N" LOC = H12;
NET "FPGA_CLK_N" IOSTANDARD = "LVDS_25";
NET "FPGA_CLK_P" LOC = G11;
NET "FPGA_CLK_P" IOSTANDARD = "LVDS_25";
TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_N" 125 MHz HIGH 50%;
TIMESPEC TS_clk_i = PERIOD "FPGA_CLK_P" 125 MHz HIGH 50%;
NET "FPGA_CLK_N" LOC = H11;
NET "FPGA_CLK_P" LOC = G11;
##======================================
......@@ -35,103 +26,73 @@ NET "FPGA_CLK_P" LOC = G11;
##-- + UBT: LVTTL input
##-------------------
NET "LED_CTRL0" LOC = M18;
NET "LED_CTRL0" IOSTANDARD = "LVTTL";
NET "LED_CTRL0" DRIVE = "4";
NET "LED_CTRL0" SLEW = "QUIETIO";
NET "LED_CTRL0_OEN" LOC = T20;
NET "LED_CTRL0_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL0_OEN" DRIVE = "4";
NET "LED_CTRL0_OEN" SLEW = "QUIETIO";
NET "LED_CTRL1" LOC = M17;
NET "LED_CTRL1" IOSTANDARD = "LVTTL";
NET "LED_CTRL1" DRIVE = "4";
NET "LED_CTRL1" SLEW = "QUIETIO";
NET "LED_CTRL1_OEN" LOC = U19;
NET "LED_CTRL1_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL1_OEN" DRIVE = "4";
NET "LED_CTRL1_OEN" SLEW = "QUIETIO";
NET "LED_MULTICAST_2_0" LOC = P16;
NET "LED_MULTICAST_2_0" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_2_0" DRIVE = "4";
NET "LED_MULTICAST_2_0" SLEW = "QUIETIO";
NET "LED_MULTICAST_3_1" LOC = P17;
NET "LED_MULTICAST_3_1" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_3_1" DRIVE = "4";
NET "LED_MULTICAST_3_1" SLEW = "QUIETIO";
NET "LED_WR_GMT_TTL_TTLN" LOC = N16;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = "LVTTL";
NET "LED_WR_GMT_TTL_TTLN" DRIVE = "4";
NET "LED_WR_GMT_TTL_TTLN" SLEW = "QUIETIO";
NET "LED_WR_LINK_SYSERROR" LOC = R15;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = "LVTTL";
NET "LED_WR_LINK_SYSERROR" DRIVE = "4";
NET "LED_WR_LINK_SYSERROR" SLEW = "QUIETIO";
NET "LED_WR_OK_SYSPW" LOC = R16;
NET "LED_WR_OK_SYSPW" IOSTANDARD = "LVTTL";
NET "LED_WR_OK_SYSPW" DRIVE = "4";
NET "LED_WR_OK_SYSPW" SLEW = "QUIETIO";
NET "LED_WR_OWNADDR_I2C" LOC = N15;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
NET "LED_WR_OWNADDR_I2C" DRIVE = "4";
NET "LED_WR_OWNADDR_I2C" SLEW = "QUIETIO";
##-------------------
##-- Front channel LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_FRONT_LED1_N" LOC = H5;
NET "PULSE_FRONT_LED1_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED1_N" DRIVE = "4";
NET "PULSE_FRONT_LED1_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED2_N" LOC = J6;
NET "PULSE_FRONT_LED2_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED2_N" DRIVE = "4";
NET "PULSE_FRONT_LED2_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED3_N" LOC = K6;
NET "PULSE_FRONT_LED3_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED3_N" DRIVE = "4";
NET "PULSE_FRONT_LED3_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED4_N" LOC = K5;
NET "PULSE_FRONT_LED4_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED4_N" DRIVE = "4";
NET "PULSE_FRONT_LED4_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED5_N" LOC = M7;
NET "PULSE_FRONT_LED5_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED5_N" DRIVE = "4";
NET "PULSE_FRONT_LED5_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED6_N" LOC = M6;
NET "PULSE_FRONT_LED6_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED6_N" DRIVE = "4";
NET "PULSE_FRONT_LED6_N" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[1]" LOC = H5;
NET "PULSE_FRONT_LED_N[1]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[1]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[1]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[2]" LOC = J6;
NET "PULSE_FRONT_LED_N[2]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[2]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[2]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[3]" LOC = K6;
NET "PULSE_FRONT_LED_N[3]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[3]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[3]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[4]" LOC = K5;
NET "PULSE_FRONT_LED_N[4]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[4]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[4]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[5]" LOC = M7;
NET "PULSE_FRONT_LED_N[5]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[5]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[5]" SLEW = "QUIETIO";
NET "PULSE_FRONT_LED_N[6]" LOC = M6;
NET "PULSE_FRONT_LED_N[6]" IOSTANDARD = "LVCMOS33";
NET "PULSE_FRONT_LED_N[6]" DRIVE = "4";
NET "PULSE_FRONT_LED_N[6]" SLEW = "QUIETIO";
##-------------------
##-- Rear LEDs
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "PULSE_REAR_LED1_N" LOC = AB17;
NET "PULSE_REAR_LED1_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED1_N" DRIVE = "4";
NET "PULSE_REAR_LED1_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED2_N" LOC = AB19;
NET "PULSE_REAR_LED2_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED2_N" DRIVE = "4";
NET "PULSE_REAR_LED2_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED3_N" LOC = AA16;
NET "PULSE_REAR_LED3_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED3_N" DRIVE = "4";
NET "PULSE_REAR_LED3_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED4_N" LOC = AA18;
NET "PULSE_REAR_LED4_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED4_N" DRIVE = "4";
NET "PULSE_REAR_LED4_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED5_N" LOC = AB16;
NET "PULSE_REAR_LED5_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED5_N" DRIVE = "4";
NET "PULSE_REAR_LED5_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED6_N" LOC = AB18;
NET "PULSE_REAR_LED6_N" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED6_N" DRIVE = "4";
NET "PULSE_REAR_LED6_N" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[1]" LOC = AB17;
NET "PULSE_REAR_LED_N[1]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[1]" DRIVE = "4";
NET "PULSE_REAR_LED_N[1]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[2]" LOC = AB19;
NET "PULSE_REAR_LED_N[2]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[2]" DRIVE = "4";
NET "PULSE_REAR_LED_N[2]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[3]" LOC = AA16;
NET "PULSE_REAR_LED_N[3]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[3]" DRIVE = "4";
NET "PULSE_REAR_LED_N[3]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[4]" LOC = AA18;
NET "PULSE_REAR_LED_N[4]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[4]" DRIVE = "4";
NET "PULSE_REAR_LED_N[4]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[5]" LOC = AB16;
NET "PULSE_REAR_LED_N[5]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[5]" DRIVE = "4";
NET "PULSE_REAR_LED_N[5]" SLEW = "QUIETIO";
NET "PULSE_REAR_LED_N[6]" LOC = AB18;
NET "PULSE_REAR_LED_N[6]" IOSTANDARD = "LVCMOS33";
NET "PULSE_REAR_LED_N[6]" DRIVE = "4";
NET "PULSE_REAR_LED_N[6]" SLEW = "QUIETIO";
##-------------------
......@@ -139,30 +100,30 @@ NET "PULSE_REAR_LED6_N" LOC = AB18;
##--
##-- + ACT family: CMOS/TTL 3.3V inputs
##-------------------
NET "FPGA_INPUT_TTL1_N" LOC = T2;
NET "FPGA_INPUT_TTL1_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL2_N" LOC = U3;
NET "FPGA_INPUT_TTL2_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL3_N" LOC = V5;
NET "FPGA_INPUT_TTL3_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL4_N" LOC = W4;
NET "FPGA_INPUT_TTL4_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL5_N" LOC = T6;
NET "FPGA_INPUT_TTL5_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL6_N" LOC = T3;
NET "FPGA_INPUT_TTL6_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL1" LOC = C1;
NET "FPGA_OUT_TTL1" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL2" LOC = F2;
NET "FPGA_OUT_TTL2" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL3" LOC = F5;
NET "FPGA_OUT_TTL3" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL4" LOC = H4;
NET "FPGA_OUT_TTL4" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL5" LOC = J4;
NET "FPGA_OUT_TTL5" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL6" LOC = H2;
NET "FPGA_OUT_TTL6" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[1]" LOC = T2;
NET "FPGA_INPUT_TTL_N[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[2]" LOC = U3;
NET "FPGA_INPUT_TTL_N[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[3]" LOC = V5;
NET "FPGA_INPUT_TTL_N[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[4]" LOC = W4;
NET "FPGA_INPUT_TTL_N[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[5]" LOC = T6;
NET "FPGA_INPUT_TTL_N[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_INPUT_TTL_N[6]" LOC = T3;
NET "FPGA_INPUT_TTL_N[6]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[1]" LOC = C1;
NET "FPGA_OUT_TTL[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[2]" LOC = F2;
NET "FPGA_OUT_TTL[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[3]" LOC = F5;
NET "FPGA_OUT_TTL[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[4]" LOC = H4;
NET "FPGA_OUT_TTL[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[5]" LOC = J4;
NET "FPGA_OUT_TTL[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_OUT_TTL[6]" LOC = H2;
NET "FPGA_OUT_TTL[6]" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Bottomly allocated GPIOs
##--
......@@ -172,22 +133,22 @@ NET "FPGA_OUT_TTL6" LOC = H2;
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
NET "INV_IN_1_N" LOC = V2;
NET "INV_IN_1_N" IOSTANDARD = "LVCMOS33";
NET "INV_IN_2_N" LOC = W3;
NET "INV_IN_2_N" IOSTANDARD = "LVCMOS33";
NET "INV_IN_3_N" LOC = Y2;
NET "INV_IN_3_N" IOSTANDARD = "LVCMOS33";
NET "INV_IN_4_N" LOC = AA2;
NET "INV_IN_4_N" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_1" LOC = J3;
NET "INV_OUT_1" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_2" LOC = L3;
NET "INV_OUT_2" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_3" LOC = M3;
NET "INV_OUT_3" IOSTANDARD = "LVCMOS33";
NET "INV_OUT_4" LOC = P2;
NET "INV_OUT_4" IOSTANDARD = "LVCMOS33";
NET "INV_IN_N[1]" LOC = V2;
NET "INV_IN_N[1]" IOSTANDARD = "LVCMOS33";
NET "INV_IN_N[2]" LOC = W3;
NET "INV_IN_N[2]" IOSTANDARD = "LVCMOS33";
NET "INV_IN_N[3]" LOC = Y2;
NET "INV_IN_N[3]" IOSTANDARD = "LVCMOS33";
NET "INV_IN_N[4]" LOC = AA2;
NET "INV_IN_N[4]" IOSTANDARD = "LVCMOS33";
NET "INV_OUT[1]" LOC = J3;
NET "INV_OUT[1]" IOSTANDARD = "LVCMOS33";
NET "INV_OUT[2]" LOC = L3;
NET "INV_OUT[2]" IOSTANDARD = "LVCMOS33";
NET "INV_OUT[3]" LOC = M3;
NET "INV_OUT[3]" IOSTANDARD = "LVCMOS33";
NET "INV_OUT[4]" LOC = P2;
NET "INV_OUT[4]" IOSTANDARD = "LVCMOS33";
##======================================
......@@ -198,30 +159,30 @@ NET "INV_OUT_4" LOC = P2;
##-- Schematics name: FPGA_BLO_IN_*
##---- renamed to FPGA_BLO_IN[*]
##-------------------
NET "FPGA_BLO_IN_1" LOC = Y9;
NET "FPGA_BLO_IN_1" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_2" LOC = AA10;
NET "FPGA_BLO_IN_2" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_3" LOC = W12;
NET "FPGA_BLO_IN_3" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_4" LOC = AA6;
NET "FPGA_BLO_IN_4" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_5" LOC = Y7;
NET "FPGA_BLO_IN_5" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN_6" LOC = AA8;
NET "FPGA_BLO_IN_6" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO1" LOC = W9;
NET "FPGA_TRIG_BLO1" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO2" LOC = T10;
NET "FPGA_TRIG_BLO2" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO3" LOC = V7;
NET "FPGA_TRIG_BLO3" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO4" LOC = U9;
NET "FPGA_TRIG_BLO4" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO5" LOC = T8;
NET "FPGA_TRIG_BLO5" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO6" LOC = R9;
NET "FPGA_TRIG_BLO6" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[1]" LOC = Y9;
NET "FPGA_BLO_IN[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[2]" LOC = AA10;
NET "FPGA_BLO_IN[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[3]" LOC = W12;
NET "FPGA_BLO_IN[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[4]" LOC = AA6;
NET "FPGA_BLO_IN[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[5]" LOC = Y7;
NET "FPGA_BLO_IN[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_BLO_IN[6]" LOC = AA8;
NET "FPGA_BLO_IN[6]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[1]" LOC = W9;
NET "FPGA_TRIG_BLO[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[2]" LOC = T10;
NET "FPGA_TRIG_BLO[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[3]" LOC = V7;
NET "FPGA_TRIG_BLO[3]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[4]" LOC = U9;
NET "FPGA_TRIG_BLO[4]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[5]" LOC = T8;
NET "FPGA_TRIG_BLO[5]" IOSTANDARD = "LVCMOS33";
NET "FPGA_TRIG_BLO[6]" LOC = R9;
NET "FPGA_TRIG_BLO[6]" IOSTANDARD = "LVCMOS33";
##======================================
##-- VME CONNECTOR SIGNALS
......@@ -256,16 +217,16 @@ NET "SDA_OE" LOC = J19;
##--
##-- + UBT: LVTTL input
##-------------------
NET "FPGA_GA0" LOC = H20;
NET "FPGA_GA0" IOSTANDARD = "LVTTL";
NET "FPGA_GA1" LOC = J20;
NET "FPGA_GA1" IOSTANDARD = "LVTTL";
NET "FPGA_GA2" LOC = K19;
NET "FPGA_GA2" IOSTANDARD = "LVTTL";
NET "FPGA_GA3" LOC = K20;
NET "FPGA_GA3" IOSTANDARD = "LVTTL";
NET "FPGA_GA4" LOC = L19;
NET "FPGA_GA4" IOSTANDARD = "LVTTL";
NET "FPGA_GA[0]" LOC = H20;
NET "FPGA_GA[0]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[1]" LOC = J20;
NET "FPGA_GA[1]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[2]" LOC = K19;
NET "FPGA_GA[2]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[3]" LOC = K20;
NET "FPGA_GA[3]" IOSTANDARD = "LVTTL";
NET "FPGA_GA[4]" LOC = L19;
NET "FPGA_GA[4]" IOSTANDARD = "LVTTL";
NET "FPGA_GAP" LOC = H19;
NET "FPGA_GAP" IOSTANDARD = "LVTTL";
##-------------------
......@@ -281,63 +242,63 @@ NET "FPGA_PROM_MOSI" LOC = AB20;
NET "FPGA_PROM_MOSI" IOSTANDARD = "LVTTL";
##======================================
##-- WHITE RABBIT
##======================================
##-------------------
##-- Thermo for UID
##-------------------
NET "THERMOMETER" LOC = B1;
NET "THERMOMETER" IOSTANDARD = "LVCMOS25";
##-------------------
##-- DACs control
##--
##-- + CMOS 3.3V input
##-------------------
NET "FPGA_PLLDAC1_DIN" LOC = AB14;
NET "FPGA_PLLDAC1_DIN" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC1_SCLK" LOC = AA14;
NET "FPGA_PLLDAC1_SCLK" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC1_SYNC_N" LOC = AB15;
NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_DIN" LOC = W14;
NET "FPGA_PLLDAC2_DIN" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_SCLK" LOC = Y14;
NET "FPGA_PLLDAC2_SCLK" IOSTANDARD = "LVCMOS25";
NET "FPGA_PLLDAC2_SYNC_N" LOC = W13;
NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
##-------------------
##-- SFP connection
##-------------------
NET "FPGA_SFP_LOS" LOC = G3;
NET "FPGA_SFP_LOS" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_MOD_DEF0" LOC = K8;
NET "FPGA_SFP_MOD_DEF0" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_RATE_SELECT" LOC = C4;
NET "FPGA_SFP_RATE_SELECT" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_MOD_DEF1" LOC = G4;
NET "FPGA_SFP_MOD_DEF1" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_MOD_DEF2" LOC = F3;
NET "FPGA_SFP_MOD_DEF2" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_TX_DISABLE" LOC = E4;
NET "FPGA_SFP_TX_DISABLE" IOSTANDARD = "LVCMOS33";
NET "FPGA_SFP_TX_FAULT" LOC = D2;
NET "FPGA_SFP_TX_FAULT" IOSTANDARD = "LVCMOS33";
##-------------------
##-- FPGA MGT lines
##-------------------
NET "FPGAMGTCLK0_P" LOC = A10;
NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
NET "FPGAMGTCLK0_N" LOC = B10;
NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
NET "MGTSFPRX0_P" LOC = D7;
NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
NET "MGTSFPRX0_N" LOC = C7;
NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
NET "MGTSFPTX0_P" LOC = B6;
NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
NET "MGTSFPTX0_N" LOC = A6;
NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
###======================================
###-- WHITE RABBIT
###======================================
###-------------------
###-- Thermo for UID
###-------------------
#NET "THERMOMETER" LOC = B1;
# NET "THERMOMETER" IOSTANDARD = "LVCMOS25";
###-------------------
###-- DACs control
###--
###-- + CMOS 3.3V input
###-------------------
#NET "FPGA_PLLDAC1_DIN" LOC = AB14;
# NET "FPGA_PLLDAC1_DIN" IOSTANDARD = "LVCMOS25";
#NET "FPGA_PLLDAC1_SCLK" LOC = AA14;
# NET "FPGA_PLLDAC1_SCLK" IOSTANDARD = "LVCMOS25";
#NET "FPGA_PLLDAC1_SYNC_N" LOC = AB15;
# NET "FPGA_PLLDAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
#NET "FPGA_PLLDAC2_DIN" LOC = W14;
# NET "FPGA_PLLDAC2_DIN" IOSTANDARD = "LVCMOS25";
#NET "FPGA_PLLDAC2_SCLK" LOC = Y14;
# NET "FPGA_PLLDAC2_SCLK" IOSTANDARD = "LVCMOS25";
#NET "FPGA_PLLDAC2_SYNC_N" LOC = W13;
# NET "FPGA_PLLDAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
###-------------------
###-- SFP connection
###-------------------
#NET "FPGA_SFP_LOS" LOC = G3;
# NET "FPGA_SFP_LOS" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SFP_MOD_DEF0" LOC = K8;
# NET "FPGA_SFP_MOD_DEF0" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SFP_RATE_SELECT" LOC = C4;
# NET "FPGA_SFP_RATE_SELECT" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SFP_MOD_DEF1" LOC = G4;
# NET "FPGA_SFP_MOD_DEF1" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SFP_MOD_DEF2" LOC = F3;
# NET "FPGA_SFP_MOD_DEF2" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SFP_TX_DISABLE" LOC = E4;
# NET "FPGA_SFP_TX_DISABLE" IOSTANDARD = "LVCMOS33";
#NET "FPGA_SFP_TX_FAULT" LOC = D2;
# NET "FPGA_SFP_TX_FAULT" IOSTANDARD = "LVCMOS33";
###-------------------
###-- FPGA MGT lines
###-------------------
#NET "FPGAMGTCLK0_P" LOC = A10;
# NET "FPGAMGTCLK0_P" IOSTANDARD = "LVDS_12";
#NET "FPGAMGTCLK0_N" LOC = B10;
# NET "FPGAMGTCLK0_N" IOSTANDARD = "LVDS_12";
#NET "MGTSFPRX0_P" LOC = D7;
# NET "MGTSFPRX0_P" IOSTANDARD = "LVDS_12";
#NET "MGTSFPRX0_N" LOC = C7;
# NET "MGTSFPRX0_N" IOSTANDARD = "LVDS_12";
#NET "MGTSFPTX0_P" LOC = B6;
# NET "MGTSFPTX0_P" IOSTANDARD = "LVDS_12";
#NET "MGTSFPTX0_N" LOC = A6;
# NET "MGTSFPTX0_N" IOSTANDARD = "LVDS_12";
##======================================
......@@ -368,65 +329,65 @@ NET "FPGA_INV_OE" LOC = P6;
##-- Schematics name EXTRA_SWITCH_*
##---- renamed to EXTRA_SWITCH[*]
##-------------------
NET "EXTRA_SWITCH_1" LOC = F22;
NET "EXTRA_SWITCH_1" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_2" LOC = G22;
NET "EXTRA_SWITCH_2" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_3" LOC = H21;
NET "EXTRA_SWITCH_3" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_4" LOC = H22;
NET "EXTRA_SWITCH_4" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_5" LOC = J22;
NET "EXTRA_SWITCH_5" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_6" LOC = K21;
NET "EXTRA_SWITCH_6" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH_7" LOC = K22;
NET "EXTRA_SWITCH_7" IOSTANDARD = "LVCMOS33";
NET "TTL/INV_TTL_N" LOC = L22;
NET "TTL/INV_TTL_N" IOSTANDARD = "LVCMOS33";
NET "EXTRA_SWITCH[1]" LOC = F22;
NET "EXTRA_SWITCH[1]" IOSTANDARD = "LVCMOS33";
# NET "EXTRA_SWITCH[2]" LOC = G22;
# NET "EXTRA_SWITCH[2]" IOSTANDARD = "LVCMOS33";
# NET "EXTRA_SWITCH[3]" LOC = H21;
# NET "EXTRA_SWITCH[3]" IOSTANDARD = "LVCMOS33";
# NET "EXTRA_SWITCH[4]" LOC = H22;
# NET "EXTRA_SWITCH[4]" IOSTANDARD = "LVCMOS33";
# NET "EXTRA_SWITCH[5]" LOC = J22;
# NET "EXTRA_SWITCH[5]" IOSTANDARD = "LVCMOS33";
# NET "EXTRA_SWITCH[6]" LOC = K21;
# NET "EXTRA_SWITCH[6]" IOSTANDARD = "LVCMOS33";
# NET "EXTRA_SWITCH[7]" LOC = K22;
# NET "EXTRA_SWITCH[7]" IOSTANDARD = "LVCMOS33";
NET "LEVEL" LOC = L22;
NET "LEVEL" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Motherboard and piggyback IDs
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "FPGA_RTMM0_N" LOC = V21;
NET "FPGA_RTMM0_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM1_N" LOC = V22;
NET "FPGA_RTMM1_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM2_N" LOC = U22;
NET "FPGA_RTMM2_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP0_N" LOC = W22;
NET "FPGA_RTMP0_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP1_N" LOC = Y22;
NET "FPGA_RTMP1_N" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP2_N" LOC = Y21;
NET "FPGA_RTMP2_N" IOSTANDARD = "LVCMOS33";
##-------------------
##-- General purpose
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "FPGA_HEADER_OUT_N1" LOC = F15;
NET "FPGA_HEADER_OUT_N1" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N2" LOC = F16;
NET "FPGA_HEADER_OUT_N2" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N3" LOC = F17;
NET "FPGA_HEADER_OUT_N3" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N4" LOC = F14;
NET "FPGA_HEADER_OUT_N4" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N5" LOC = H14;
NET "FPGA_HEADER_OUT_N5" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_OUT_N6" LOC = H13;
NET "FPGA_HEADER_OUT_N6" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N1" LOC = A17;
NET "FPGA_HEADER_IN_N1" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N2" LOC = A18;
NET "FPGA_HEADER_IN_N2" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N3" LOC = B18;
NET "FPGA_HEADER_IN_N3" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N4" LOC = A19;
NET "FPGA_HEADER_IN_N4" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N5" LOC = A20;
NET "FPGA_HEADER_IN_N5" IOSTANDARD = "LVCMOS33";
NET "FPGA_HEADER_IN_N6" LOC = B20;
NET "FPGA_HEADER_IN_N6" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM_N[0]" LOC = V21;
NET "FPGA_RTMM_N[0]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM_N[1]" LOC = V22;
NET "FPGA_RTMM_N[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMM_N[2]" LOC = U22;
NET "FPGA_RTMM_N[2]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP_N[0]" LOC = W22;
NET "FPGA_RTMP_N[0]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "FPGA_RTMP_N[1]" IOSTANDARD = "LVCMOS33";
NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "FPGA_RTMP_N[2]" IOSTANDARD = "LVCMOS33";
###-------------------
###-- General purpose
###--
###-- + ACT: CMOS 3.3V input
###-------------------
# NET "FPGA_HEADER_OUT_N[1]" LOC = F15;
# NET "FPGA_HEADER_OUT_N[1]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_OUT_N[2]" LOC = F16;
# NET "FPGA_HEADER_OUT_N[2]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_OUT_N[3]" LOC = F17;
# NET "FPGA_HEADER_OUT_N[3]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_OUT_N[4]" LOC = F14;
# NET "FPGA_HEADER_OUT_N[4]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_OUT_N[5]" LOC = H14;
# NET "FPGA_HEADER_OUT_N[5]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_OUT_N[6]" LOC = H13;
# NET "FPGA_HEADER_OUT_N[6]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_IN_N[1]" LOC = A17;
# NET "FPGA_HEADER_IN_N[1]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_IN_N[2]" LOC = A18;
# NET "FPGA_HEADER_IN_N[2]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_IN_N[3]" LOC = B18;
# NET "FPGA_HEADER_IN_N[3]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_IN_N[4]" LOC = A19;
# NET "FPGA_HEADER_IN_N[4]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_IN_N[5]" LOC = A20;
# NET "FPGA_HEADER_IN_N[5]" IOSTANDARD = "LVCMOS33";
# NET "FPGA_HEADER_IN_N[6]" LOC = B20;
# NET "FPGA_HEADER_IN_N[6]" IOSTANDARD = "LVCMOS33";
hdl/IMAGES/image1/project/image1.gise
View file @ accb11b0
......@@ -26,10 +26,9 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="basic_trigger_top.vhi"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="i2c_slave_top.vhi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="image1_top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="image1_top.cmd_log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="image1_top.fdo"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="image1_top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="image1_top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="image1_top.ngd"/>
......@@ -47,7 +46,7 @@
<file xil_pn:fileType="FILE_HTML" xil_pn:name="image1_top_summary.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="image1_top_tb.fdo"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_xst.xrpt"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="m25p32_top.vhi"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
......@@ -56,11 +55,10 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1354289428" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1354289428">
<transform xil_pn:end_ts="1359108425" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1359108425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1355240543" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1355240543">
<transform xil_pn:end_ts="1359109243" xil_pn:in_ck="-7672365651252725296" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1359109243">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
......@@ -68,6 +66,8 @@
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
......@@ -95,24 +95,27 @@
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_core.vhd"/>
<outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_top.vhd"/>
<outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
<outfile xil_pn:name="../top/image1_top.vhd"/>
</transform>
<transform xil_pn:end_ts="1354289428" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="239257099518693425" xil_pn:start_ts="1354289428">
<transform xil_pn:end_ts="1359108983" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="239257099518693425" xil_pn:start_ts="1359108983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354289428" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3020523367752079697" xil_pn:start_ts="1354289428">
<transform xil_pn:end_ts="1359108983" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3020523367752079697" xil_pn:start_ts="1359108983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354289428" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1354289428">
<transform xil_pn:end_ts="1359108425" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1359108425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1355240543" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1355240543">
<transform xil_pn:end_ts="1359109243" xil_pn:in_ck="-7672365651252725296" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1359109243">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
......@@ -120,6 +123,8 @@
<outfile xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
......@@ -147,89 +152,21 @@
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_core.vhd"/>
<outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_top.vhd"/>
<outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
<outfile xil_pn:name="../top/image1_top.vhd"/>
</transform>
<transform xil_pn:end_ts="1355302790" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1355302789">
<transform xil_pn:end_ts="1359109244" xil_pn:in_ck="-7672365651252725296" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1359109243">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="image1_top_tb.fdo"/>
<outfile xil_pn:name="vsim.wlf"/>
<outfile xil_pn:name="work"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1353947909" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1353947909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354289325" xil_pn:in_ck="-545934943622296316" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1354289231">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="image1_top.lso"/>
<outfile xil_pn:name="image1_top.ngc"/>
<outfile xil_pn:name="image1_top.ngr"/>
<outfile xil_pn:name="image1_top.prj"/>
<outfile xil_pn:name="image1_top.stx"/>
<outfile xil_pn:name="image1_top.syr"/>
<outfile xil_pn:name="image1_top.xst"/>
<outfile xil_pn:name="image1_top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1354033300" xil_pn:in_ck="-7461616560160808584" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1354033300">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354033381" xil_pn:in_ck="4649869214785825988" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1354033375">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1354033402" xil_pn:in_ck="4649869214785825989" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1354033381">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
</generated_project>
hdl/IMAGES/image1/project/image1.xise
View file @ accb11b0
......@@ -15,29 +15,52 @@
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../rtl/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<file xil_pn:name="../constraints/V2/BloV2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../rtl/image1_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../rtl/image1_led_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../rtl/image1_wrappers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../top/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
......@@ -60,13 +83,29 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
......@@ -83,22 +122,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
......@@ -112,57 +135,54 @@
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../constraints/FPGAbank.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../test/image1_top_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../test/image1_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
</files>
......@@ -178,7 +198,7 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -195,6 +215,7 @@
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -209,9 +230,9 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Do File Behavioral" xil_pn:value="waveform/wave.do" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
......@@ -227,7 +248,7 @@
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -266,6 +287,7 @@
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -275,18 +297,19 @@
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|image1_top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/image1_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../top/image1_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/image1_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -303,8 +326,8 @@
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Fit Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -315,7 +338,6 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Fit UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -336,11 +358,20 @@
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -370,8 +401,7 @@
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="This is the project containing all the requiered functionality for Blocking board." xil_pn:valueState="non-default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -402,10 +432,17 @@
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
......@@ -415,12 +452,20 @@
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -441,6 +486,18 @@
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -449,11 +506,12 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/13.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -476,15 +534,13 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-21T17:40:19" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5445B05288FBBDDF0B997F95368EC1BD" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-24T15:54:01" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0C474E515E59579E259F7506857F3A8C" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/image1_top" xil_pn:name="../constraints/FPGAbank.ucf"/>
</bindings>
<bindings/>
<libraries/>
......
hdl/IMAGES/image1/project/waveform/wave.do
View file @ accb11b0
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider image1_top
add wave -noupdate /image1_top_tb/uut/pll_base_inst/LOCKED
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/s_clk
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/s_rst
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_link_up_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_pps_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_wr_ok_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_pw_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_err_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_led_ttl_o
add wave -noupdate /image1_top_tb/s_rst_SYS_A
add wave -noupdate -group {Front Panel} /image1_top_tb/s_pulse_led
add wave -noupdate -group {Front Panel} /image1_top_tb/s_pulse_i
add wave -noupdate -group {Front Panel} /image1_top_tb/s_pulse_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_inv_i
add wave -noupdate -group {Front Panel} /image1_top_tb/s_inv_o
add wave -noupdate -expand -group I2C /image1_top_tb/s_sda_slave_oen
add wave -noupdate -expand -group I2C /image1_top_tb/s_scl_slave_oen
add wave -noupdate -expand -group I2C -expand /image1_top_tb/s_I2C_slave_i
add wave -noupdate -expand -group I2C -expand /image1_top_tb/s_I2C_slave_o
add wave -noupdate -expand -group I2C /image1_top_tb/s_FPGA_GA
add wave -noupdate -expand -group I2C /image1_top_tb/s_FPGA_GAP
add wave -noupdate -group I2C /image1_top_tb/s_sda_slave_oen
add wave -noupdate -group I2C /image1_top_tb/s_scl_slave_oen
add wave -noupdate -group I2C /image1_top_tb/s_I2C_slave_i
add wave -noupdate -group I2C /image1_top_tb/s_I2C_slave_o
add wave -noupdate -group I2C /image1_top_tb/s_FPGA_GA
add wave -noupdate -group I2C /image1_top_tb/s_FPGA_GAP
add wave -noupdate -group SPI /image1_top_tb/s_SPI_master_i
add wave -noupdate -group SPI -expand /image1_top_tb/s_SPI_master_o
add wave -noupdate -group CTRL /image1_top_tb/s_fpga_en
......@@ -29,133 +21,92 @@ add wave -noupdate -group CTRL /image1_top_tb/switch_i
add wave -noupdate -group CTRL /image1_top_tb/s_RTM_id_i
add wave -noupdate -group CTRL /image1_top_tb/manual_rst_n_o
add wave -noupdate -radix hexadecimal /image1_top_tb/s_i2c_addr_op
add wave -noupdate -divider {Status LEDs}
add wave -noupdate /image1_top_tb/uut/inst_image1_core/inst_bicolor_led_ctrl/rst_n_i
add wave -noupdate /image1_top_tb/uut/CLK20_VCXO
add wave -noupdate /image1_top_tb/uut/inst_image1_core/led_array_o
add wave -noupdate /image1_top_tb/uut/inst_image1_core/s_led_state_array
add wave -noupdate -expand /image1_top_tb/uut/inst_image1_core/s_leds_array_image1
add wave -noupdate -divider wb_xbar
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_wb_crossbar/clk_sys_i
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_wb_crossbar/rst_n_i
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_wb_crossbar/slave_i
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_wb_crossbar/master_i
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_wb_crossbar/slave_o
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_wb_crossbar/master_o
add wave -noupdate /image1_top_tb/wb_clk
add wave -noupdate -group wb_slave_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/slave_i
add wave -noupdate -group wb_slave_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/slave_o
add wave -noupdate -group wb_master_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/master_i
add wave -noupdate -group wb_master_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/master_o
add wave -noupdate -group wb_master_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/master_ie
add wave -noupdate -group wb_master_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/master_oe
add wave -noupdate -divider i2c_slave
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/wb_clk
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/wb_rst_i
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm
add wave -noupdate /image1_top_tb/uut/inst_i2c_slave/inst_i2c_regs/i2c_master_WB_BASIC_fsm
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_CTR0
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_LT
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/s_CTR0_slv
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/s_LT_slv
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_DRXA_slv
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_DRXB_slv
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_regs/s_DTX
add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/scl_i
add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/sda_i
add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/sda_o
add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/sda_oen
add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/scl_oen
add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/scl_o
add wave -noupdate -expand -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_stb_o
add wave -noupdate -expand -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_cyc_o
add wave -noupdate -expand -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_sel_o
add wave -noupdate -expand -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_we_o
add wave -noupdate -expand -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_data_o
add wave -noupdate -expand -group wb_master_i2c_o -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/wb_master_addr_o
add wave -noupdate -expand -group wb_master_i2c_i -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/wb_master_data_i
add wave -noupdate -expand -group wb_master_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_master_ack_i
add wave -noupdate -expand -group wb_master_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_master_rty_i
add wave -noupdate -expand -group wb_master_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_master_err_i
add wave -noupdate -group wb_slave_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_slave_stb_i
add wave -noupdate -group wb_slave_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_slave_cyc_i
add wave -noupdate -group wb_slave_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_slave_sel_i
add wave -noupdate -group wb_slave_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_slave_we_i
add wave -noupdate -group wb_slave_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_slave_data_i
add wave -noupdate -group wb_slave_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_slave_addr_i
add wave -noupdate -group wb_slave_i2c_i /image1_top_tb/uut/inst_i2c_slave/i2c_addr_i
add wave -noupdate -group wb_slave_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_slave_data_o
add wave -noupdate -group wb_slave_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_slave_ack_o
add wave -noupdate -group wb_slave_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_slave_rty_o
add wave -noupdate -group wb_slave_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_slave_err_o
add wave -noupdate -group {i2c counters} /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt
add wave -noupdate -group {i2c counters} /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_bit_done
add wave -noupdate -group {i2c counters} /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_rst
add wave -noupdate -group {i2c counters} /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt
add wave -noupdate -group {i2c counters} /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_en
add wave -noupdate -group {i2c counters} /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_rst
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/s_pf_wb_data
add wave -noupdate /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_sda_o
add wave -noupdate /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/inst_i2c_bit/done_o
add wave -noupdate /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/inst_i2c_bit/start_o
add wave -noupdate /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/inst_i2c_bit/pause_o
add wave -noupdate /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/inst_i2c_bit/rcved_o
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/pf_wb_addr_o
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/rd_done_o
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/wr_done_o
add wave -noupdate /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm
add wave -noupdate /image1_top_tb/s_I2C_regs
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_ack_i
add wave -noupdate -group wb_master -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_addr_o
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_cyc_o
add wave -noupdate -group wb_master -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_data_i
add wave -noupdate -group wb_master -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_data_o
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_err_i
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_rty_i
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_sel_o
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_stb_o
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_we_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_ack_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_addr_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_cyc_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_data_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_data_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_err_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_rty_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_sel_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_stb_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_we_i
add wave -noupdate -divider m25p32
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_m25p32/miso_word_rcv
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_m25p32/op_finished_o
add wave -noupdate /image1_top_tb/uut/inst_image1_core/inst_m25p32/inst_m25p32_core/s_MEM_fsm
add wave -noupdate /image1_top_tb/s_M25P32_regs
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_we_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_stb_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_sel_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_rty_o
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_rst_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_err_o
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_data_o
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_data_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_cyc_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_clk
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_addr_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_ack_o
add wave -noupdate -radix hexadecimal /image1_top_tb/i2c_driver/rd_data_o
add wave -noupdate /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_FMI
add wave -noupdate /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_SR_m25p32
add wave -noupdate -radix hexadecimal -subitemconfig {/image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(63) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(62) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(61) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(60) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(59) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(58) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(57) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(56) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(55) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(54) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(53) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(52) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(51) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(50) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(49) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(48) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(47) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(46) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(45) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(44) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(43) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(42) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(41) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(40) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(39) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(38) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(37) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(36) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(35) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(34) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(33) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(32) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(31) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(30) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(29) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(28) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(27) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(26) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(25) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(24) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(23) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(22) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(21) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(20) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(19) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(18) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(17) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(16) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(15) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(14) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(13) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(12) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(11) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(10) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(9) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(8) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(7) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(6) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(5) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(4) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(3) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(2) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(1) {-radix hexadecimal} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page(0) {-radix hexadecimal}} /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_wr_page
add wave -noupdate /image1_top_tb/uut/inst_m25p32/inst_m25p32_regs/s_rd_word
add wave -noupdate -group spi /image1_top_tb/uut/inst_m25p32/prom_cclk_o
add wave -noupdate -group spi /image1_top_tb/uut/inst_m25p32/prom_cs0_b_n_o
add wave -noupdate -group spi /image1_top_tb/uut/inst_m25p32/prom_din_i
add wave -noupdate -group spi /image1_top_tb/uut/inst_m25p32/prom_mosi_o
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_m25p32/wb_clk
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_m25p32/wb_rst_i
add wave -noupdate -expand -group wb_slave_m25p32_i /image1_top_tb/uut/inst_m25p32/wb_stb_i
add wave -noupdate -expand -group wb_slave_m25p32_i /image1_top_tb/uut/inst_m25p32/wb_cyc_i
add wave -noupdate -expand -group wb_slave_m25p32_i /image1_top_tb/uut/inst_m25p32/wb_sel_i
add wave -noupdate -expand -group wb_slave_m25p32_i /image1_top_tb/uut/inst_m25p32/wb_we_i
add wave -noupdate -expand -group wb_slave_m25p32_i /image1_top_tb/uut/inst_m25p32/wb_addr_i
add wave -noupdate -expand -group wb_slave_m25p32_i /image1_top_tb/uut/inst_m25p32/wb_data_i
add wave -noupdate -group wb_slave_m25p32_o /image1_top_tb/uut/inst_m25p32/wb_ack_o
add wave -noupdate -group wb_slave_m25p32_o /image1_top_tb/uut/inst_m25p32/wb_data_o
add wave -noupdate -group wb_slave_m25p32_o /image1_top_tb/uut/inst_m25p32/wb_err_o
add wave -noupdate -group wb_slave_m25p32_o /image1_top_tb/uut/inst_m25p32/wb_rty_o
add wave -noupdate -divider multiboot
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/wb_clk
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/wb_rst_i
add wave -noupdate -group wb_slave_multiboot_i /image1_top_tb/uut/inst_multiboot/wb_cyc_i
add wave -noupdate -group wb_slave_multiboot_i /image1_top_tb/uut/inst_multiboot/wb_stb_i
add wave -noupdate -group wb_slave_multiboot_i /image1_top_tb/uut/inst_multiboot/wb_we_i
add wave -noupdate -group wb_slave_multiboot_i /image1_top_tb/uut/inst_multiboot/wb_sel_i
add wave -noupdate -group wb_slave_multiboot_i /image1_top_tb/uut/inst_multiboot/wb_data_i
add wave -noupdate -group wb_slave_multiboot_i /image1_top_tb/uut/inst_multiboot/wb_addr_i
add wave -noupdate -group wb_slave_multiboot_o /image1_top_tb/uut/inst_multiboot/wb_data_o
add wave -noupdate -group wb_slave_multiboot_o /image1_top_tb/uut/inst_multiboot/wb_ack_o
add wave -noupdate -group wb_slave_multiboot_o /image1_top_tb/uut/inst_multiboot/wb_err_o
add wave -noupdate -group wb_slave_multiboot_o /image1_top_tb/uut/inst_multiboot/wb_rty_o
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_CTR0
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_CTR1
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_STAT
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_GBA
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA_ICAP
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_GBA_ICAP
add wave -noupdate /image1_top_tb/uut/inst_image1_core/inst_multiboot/multiboot_core_inst/s_ICAP_fsm
add wave -noupdate /image1_top_tb/s_MULTIBOOT_regs
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_we_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_stb_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_sel_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_rty_o
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_rst_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_err_o
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_data_o
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_data_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_cyc_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_clk
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_addr_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_ack_o
add wave -noupdate -divider RTM_detector
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_rtm_detector/RTMM_i
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_rtm_detector/RTMP_i
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_rtm_detector/ok_RTMM_o
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_rtm_detector/ok_RTMP_o
add wave -noupdate -divider i2c_master_driver
add wave -noupdate /image1_top_tb/i2c_driver/tb_clk
add wave -noupdate /image1_top_tb/s_rst
add wave -noupdate -expand -group i2c_driver /image1_top_tb/i2c_driver/sda_master_i
add wave -noupdate -expand -group i2c_driver /image1_top_tb/i2c_driver/sda_master_o
add wave -noupdate -expand -group i2c_driver /image1_top_tb/i2c_driver/scl_master_o
add wave -noupdate -group i2c_driver /image1_top_tb/i2c_driver/sda_master_i
add wave -noupdate -group i2c_driver /image1_top_tb/i2c_driver/sda_master_o
add wave -noupdate -group i2c_driver /image1_top_tb/i2c_driver/scl_master_o
add wave -noupdate /image1_top_tb/i2c_driver/i2c_addr_op_i
add wave -noupdate -radix hexadecimal /image1_top_tb/i2c_driver/wishbone_addr_i
add wave -noupdate -radix hexadecimal /image1_top_tb/i2c_driver/wr_data_i
add wave -noupdate -expand /image1_top_tb/s_I2C_driver_ctrl
add wave -noupdate /image1_top_tb/s_I2C_driver_ctrl
add wave -noupdate /image1_top_tb/s_I2C_driver_ctrl_done
add wave -noupdate -radix hexadecimal /image1_top_tb/i2c_driver/s_DTX
add wave -noupdate -radix hexadecimal /image1_top_tb/s_I2C_regs
add wave -noupdate -radix hexadecimal /image1_top_tb/s_wr_fw_regs_slv
add wave -noupdate -radix hexadecimal /image1_top_tb/s_wr_fw_regs
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2425212301 ps} 0}
WaveRestoreCursors {{Cursor 1} {1143379 ps} 0}
configure wave -namecolwidth 173
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -170,4 +121,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {2335607314 ps} {2597893678 ps}
WaveRestoreZoom {992183622 ps} {1000411389 ps}
hdl/IMAGES/image1/rtl/image1_core.vhd 0 → 100644
View file @ accb11b0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: image1_core.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- date: 01-12-2012
--
-- version: 0.9
--
-- description: Core of image1 for CONV-TTL-BLO V2
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library unisim;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.image1_pkg.ALL;
use work.image1_wrappers_pkg.ALL;
use work.image1_led_pkg.ALL;
use work.wishbone_pkg.ALL;
use work.bicolor_led_ctrl_pkg.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity image1_core is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (rst_n : in STD_LOGIC;
clk_20MHz_i : in STD_LOGIC;
clk_125MHz_i : in STD_LOGIC;
--! LEDs
led_array_o : out t_led_array_o;
--! I/Os for pulses
led_front_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front_n : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i_n : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
i2c_slave_i : in t_i2c_slave_i;
i2c_slave_o : out t_i2c_slave_o;
--! FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
spi_master_i : in t_spi_master_i;
spi_master_o : out t_spi_master_o;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC;--! General enable
manual_rst_n_o : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
rtm_i : in t_rtm_i);
end image1_core;
architecture Behavioral of image1_core is
type t_clocks is
record
PLL_IN : STD_LOGIC; --! 125MHz Input clock
PLL_FB_IN : STD_LOGIC;
PLL_FB_OUT : STD_LOGIC;
PLL_SYS_A : STD_LOGIC; --! 50MHz Wishbone clock
PLL_SYS_B : STD_LOGIC; --! 200MHz Pulse sampling
SYS_A : STD_LOGIC;
SYS_B : STD_LOGIC;
end record;
type t_rst is
record
PLL : STD_LOGIC_VECTOR(c_RST_PLL_CLKS - 1 downto 0);
SYS_A : STD_LOGIC_VECTOR(c_RST_A_CLKS - 1 downto 0);
SYS_B : STD_LOGIC_VECTOR(c_RST_B_CLKS - 1 downto 0);
end record;
signal s_clk : t_clocks;
signal s_rst : t_rst := (PLL => (others => '1'),
SYS_A => (others => '1'),
SYS_B => (others => '1'));
signal s_rst_n : STD_LOGIC;
signal s_locked : STD_LOGIC;
signal s_ok_RTMM : STD_LOGIC;
signal s_ok_RTMP : STD_LOGIC;
signal s_slave_i : t_wishbone_slave_in_array (c_NUM_MASTERS - 1 downto 0);
signal s_slave_o : t_wishbone_slave_out_array (c_NUM_MASTERS - 1 downto 0);
signal s_master_i : t_wishbone_master_in_array (c_NUM_SLAVES - 1 downto 0);
signal s_master_o : t_wishbone_master_out_array (c_NUM_SLAVES - 1 downto 0);
signal s_i2c_addr : STD_LOGIC_VECTOR(6 downto 0);
signal s_pulse_i_front : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_leds_array_image1 : t_leds_array;
signal s_led_state_array : t_led_state_array(
c_NB_ARRAY_LEDS - 1 downto 0);
-- signal s_check_cfg : BOOLEAN;
begin
-- s_check_cfg <= check_sys_cfg;
s_i2c_addr <= f_RENESAS_I2C_ADDRESSING(UNSIGNED(FPGA_GA));
s_leds_array_image1.top.ERR <= '1' when s_ok_RTMM = '1' AND s_ok_RTMP = '1'
else '0';
s_clk.PLL_IN <= clk_125MHz_i;
s_pulse_i_front <= not(pulse_i_front_n);
s_clk_fb_bufg : BUFG
port map (O => s_clk.PLL_FB_IN, I => s_clk.PLL_FB_OUT);
-- set up the fabric PLL_BASE to drive the BUFPLL
pll_base_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => c_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => c_CLKOUTA_DIVIDE, CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => c_CLKOUTB_DIVIDE, CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => c_CLKIN_PERIOD,
REF_JITTER => 0.010)
port map (
-- Output clocks
CLKFBOUT => s_clk.PLL_FB_OUT,
CLKOUT0 => s_clk.PLL_SYS_A,
CLKOUT1 => s_clk.PLL_SYS_B,
CLKOUT2 => open, CLKOUT3 => open,
CLKOUT4 => open, CLKOUT5 => open,
-- Status and control signals
LOCKED => s_locked, RST => s_rst.PLL(c_RST_PLL_CLKS - 1),
-- Input clock control
CLKFBIN => s_clk.PLL_FB_IN,
CLKIN => s_clk.PLL_IN);
s_clk_50M_bufg : BUFG
port map (O => s_clk.SYS_A, I => s_clk.PLL_SYS_A);
s_clk_200M_bufg : BUFG
port map (O => s_clk.SYS_B, I => s_clk.PLL_SYS_B);
--! @brief Reset chain for PLL
--! @param s_clk.PLL Wishbone clock
p_reset_PLL_chain : process(s_clk.PLL_IN) is
begin
if rising_edge(s_clk.PLL_IN) then
s_rst.PLL <= (others => '1');
s_rst.PLL(0) <= '0';
for i in 1 to c_RST_PLL_CLKS - 1 loop
s_rst.PLL(i) <= s_rst.PLL(i-1);
end loop;
if s_rst.PLL(c_RST_PLL_CLKS - 1) = '1' then
end if;
end if;
end process p_reset_PLL_chain;
--! @brief Reset chain
--! @param s_clk.SYS_A Wishbone clock
p_reset_A_chain : process(s_clk.SYS_A) is
begin
if rising_edge(s_clk.SYS_A) then
if s_locked = '0' then
s_rst.SYS_A <= (others => '1');
else
s_rst.SYS_A(0) <= '0';
for i in 1 to c_RST_A_CLKS - 1 loop
s_rst.SYS_A(i) <= s_rst.SYS_A(i-1);
end loop;
if s_rst.SYS_A(c_RST_A_CLKS - 1) = '1' then
end if;
end if;
end if;
end process p_reset_A_chain;
--! @brief Reset chain
--! @param s_clk.SYS_B System of clock domain B
p_reset_B_chain : process(s_clk.SYS_B) is
begin
if rising_edge(s_clk.SYS_B) then
if s_locked = '0' then
s_rst.SYS_B <= (others => '1');
else
s_rst.SYS_B(0) <= '0';
for i in 1 to c_RST_B_CLKS - 1 loop
s_rst.SYS_B(i) <= s_rst.SYS_B(i-1);
end loop;
if s_rst.SYS_B(c_RST_B_CLKS - 1) = '1' then
end if;
end if;
end if;
end process p_reset_B_chain;
inst_basic_trigger: basic_trigger_top
generic map(g_NUMBER_OF_CHANNELS => c_NUMBER_OF_CHANNELS,
g_CLK_PERIOD => c_CLKB_PERIOD,
g_OUTPUT_PULSE_LENGTH => c_OUTPUT_PULSE_LENGTH,
g_LED_BLINKING_LENGTH => c_LED_BLINKING_LENGTH)
port map(clk_i => s_clk.SYS_B,
rst_i => s_rst.SYS_B(c_RST_B_CLKS - 1),
led_pw_o => s_leds_array_image1.top.PWR,
led_err_o => open,
led_ttl_o => s_leds_array_image1.top.TTL_N,
fpga_o_en => fpga_o_en,
fpga_o_ttl_en => fpga_o_ttl_en,
fpga_o_inv_en => fpga_o_inv_en,
fpga_o_blo_en => fpga_o_blo_en,
level => level,
switch_i => switch_i,
manual_rst_n_o => manual_rst_n_o,
pulse_i_front => s_pulse_i_front,
pulse_o_front => pulse_o_front,
pulse_i_rear => pulse_i_rear,
pulse_o_rear => pulse_o_rear,
led_o_front => led_front_n,
led_o_rear => led_rear_n,
led_link_up_o => s_leds_array_image1.middle.WR_LINK,
led_pps_o => s_leds_array_image1.middle.WR_GMT,
led_wr_ok_o => s_leds_array_image1.middle.WR_OK,
inv_i => inv_i_n,
inv_o => inv_o);
--! We are always the slave so we disable writes into SCL pin
i2c_slave_o.SCL_OE <= '0';
-- s_slave_o(c_MASTER_I2C_SLAVE).stall;
-- s_slave_o(c_MASTER_I2C_SLAVE).int;
-- s_master_i(c_SLAVE_I2C_SLAVE).stall,
-- s_master_i(c_SLAVE_I2C_SLAVE).int,
s_slave_i(c_MASTER_I2C_SLAVE).adr(31 downto 16) <= (others => '0');
inst_i2c_slave: i2c_slave_top
port map(sda_oen => i2c_slave_o.SDA_OE,
sda_i => i2c_slave_i.SDA_I,
sda_o => i2c_slave_o.SDA_O,
scl_oen => i2c_slave_o.SCL_OE,
scl_i => i2c_slave_i.SCL_I,
scl_o => i2c_slave_o.SCL_O,
wb_clk => s_clk.SYS_A,
wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
wb_master_stb_o => s_slave_i(c_MASTER_I2C_SLAVE).stb,
wb_master_cyc_o => s_slave_i(c_MASTER_I2C_SLAVE).cyc,
wb_master_sel_o => s_slave_i(c_MASTER_I2C_SLAVE).sel,
wb_master_we_o => s_slave_i(c_MASTER_I2C_SLAVE).we,
wb_master_data_i => s_slave_o(c_MASTER_I2C_SLAVE).dat,
wb_master_data_o => s_slave_i(c_MASTER_I2C_SLAVE).dat,
wb_master_addr_o => s_slave_i(c_MASTER_I2C_SLAVE).adr(15 downto 0),
wb_master_ack_i => s_slave_o(c_MASTER_I2C_SLAVE).ack,
wb_master_rty_i => s_slave_o(c_MASTER_I2C_SLAVE).rty,
wb_master_err_i => s_slave_o(c_MASTER_I2C_SLAVE).err,
wb_slave_stb_i => s_master_o(c_SLAVE_I2C_SLAVE).stb,
wb_slave_cyc_i => s_master_o(c_SLAVE_I2C_SLAVE).cyc,
wb_slave_sel_i => s_master_o(c_SLAVE_I2C_SLAVE).sel,
wb_slave_we_i => s_master_o(c_SLAVE_I2C_SLAVE).we,
wb_slave_data_i => s_master_o(c_SLAVE_I2C_SLAVE).dat,
wb_slave_data_o => s_master_i(c_SLAVE_I2C_SLAVE).dat,
wb_slave_addr_i => s_master_o(c_SLAVE_I2C_SLAVE).adr( 5 downto 2),
wb_slave_ack_o => s_master_i(c_SLAVE_I2C_SLAVE).ack,
wb_slave_rty_o => s_master_i(c_SLAVE_I2C_SLAVE).rty,
wb_slave_err_o => s_master_i(c_SLAVE_I2C_SLAVE).err,
pf_wb_addr_o => open,
rd_done_o => open,
wr_done_o => open,
i2c_addr_i => s_i2c_addr);
inst_m25p32: m25p32_top
port map(wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
wb_clk => s_clk.SYS_A,
wb_we_i => s_master_o(c_SLAVE_M25P32).we,
wb_stb_i => s_master_o(c_SLAVE_M25P32).stb,
wb_cyc_i => s_master_o(c_SLAVE_M25P32).cyc,
wb_sel_i => s_master_o(c_SLAVE_M25P32).sel,
wb_data_i => s_master_o(c_SLAVE_M25P32).dat,
wb_data_o => s_master_i(c_SLAVE_M25P32).dat,
wb_addr_i => s_master_o(c_SLAVE_M25P32).adr( 8 downto 2),
wb_ack_o => s_master_i(c_SLAVE_M25P32).ack,
wb_rty_o => s_master_i(c_SLAVE_M25P32).rty,
wb_err_o => s_master_i(c_SLAVE_M25P32).err,
miso_word_rcv => open,
op_finished_o => open,
prom_mosi_o => spi_master_o.MOSI,
prom_cclk_o => spi_master_o.CCLK,
prom_cs0_b_n_o => spi_master_o.CSO_B_N,
prom_din_i => spi_master_i.DIN);
inst_multiboot: multiboot_top
port map(wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
wb_clk => s_clk.SYS_A,
wb_we_i => s_master_o(c_SLAVE_MULTIBOOT).we,
wb_stb_i => s_master_o(c_SLAVE_MULTIBOOT).stb,
wb_cyc_i => s_master_o(c_SLAVE_MULTIBOOT).cyc,
wb_sel_i => s_master_o(c_SLAVE_MULTIBOOT).sel,
wb_data_i => s_master_o(c_SLAVE_MULTIBOOT).dat,
wb_data_o => s_master_i(c_SLAVE_MULTIBOOT).dat,
wb_addr_i => s_master_o(c_SLAVE_MULTIBOOT).adr( 5 downto 2),
wb_ack_o => s_master_i(c_SLAVE_MULTIBOOT).ack,
wb_rty_o => s_master_i(c_SLAVE_MULTIBOOT).rty,
wb_err_o => s_master_i(c_SLAVE_MULTIBOOT).err);
s_master_i(c_SLAVE_I2C_SLAVE).stall <= '0';
s_master_i(c_SLAVE_I2C_SLAVE).int <= '0';
s_master_i(c_SLAVE_M25P32).stall <= '0';
s_master_i(c_SLAVE_M25P32).int <= '0';
s_master_i(c_SLAVE_MULTIBOOT).stall <= '0';
s_master_i(c_SLAVE_MULTIBOOT).int <= '0';
inst_wb_crossbar: xwb_crossbar
generic map(g_num_masters => c_NUM_MASTERS,
g_num_slaves => c_NUM_SLAVES,
g_registered => false,
-- Address of the slaves connected
--! It should be noted that the default address length is 32
--! In our project only 16 bits are addressable
g_address => c_addresses,
g_mask => c_masks)
port map(clk_sys_i => s_clk.SYS_A,
rst_n_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
slave_i => s_slave_i ,
slave_o => s_slave_o ,
master_i => s_master_i,
master_o => s_master_o);
--! Here are organized in the same disposition as in the front panel.
--! Take a look to image1_led_pkg.vhd for the correct order for
--! bicolor_led_ctrl
s_led_state_array(c_LED_NB_PWR) <= f_LED_STATE(c_LED_COLOR_PWR)
when s_leds_array_image1.top.PWR = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_ERR) <= f_LED_STATE(c_LED_COLOR_ERR)
when s_leds_array_image1.top.ERR = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_TTL_N) <= f_LED_STATE(c_LED_COLOR_TTL_N)
when s_leds_array_image1.top.TTL_N = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_I2C) <= f_LED_STATE(c_LED_COLOR_I2C)
when s_leds_array_image1.top.I2C = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_WR_OK) <= f_LED_STATE(c_LED_COLOR_WR_OK)
when s_leds_array_image1.middle.WR_OK = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_WR_LINK) <= f_LED_STATE(c_LED_COLOR_WR_LINK)
when s_leds_array_image1.middle.WR_LINK = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_WR_GMT) <= f_LED_STATE(c_LED_COLOR_WR_GMT)
when s_leds_array_image1.middle.WR_GMT = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_WR_ADDR) <= f_LED_STATE(c_LED_COLOR_WR_ADDR)
when s_leds_array_image1.middle.WR_ADDR = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST3) <= f_LED_STATE(c_LED_COLOR_MULTICAST3)
when s_leds_array_image1.bottom.MULTICAST(3) = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST2) <= f_LED_STATE(c_LED_COLOR_MULTICAST2)
when s_leds_array_image1.bottom.MULTICAST(2) = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST1) <= f_LED_STATE(c_LED_COLOR_MULTICAST1)
when s_leds_array_image1.bottom.MULTICAST(1) = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_MULTICAST0) <= f_LED_STATE(c_LED_COLOR_MULTICAST0)
when s_leds_array_image1.bottom.MULTICAST(0) = '1'
else f_LED_STATE(c_LED_OFF);
s_rst_n <= not(s_rst.SYS_A(c_RST_A_CLKS - 1));
inst_bicolor_led_ctrl: bicolor_led_ctrl
generic map(g_NB_COLUMN => c_NB_COLUMN,
g_NB_LINE => c_NB_LINE,
g_CLK_FREQ => 20000000,
g_REFRESH_RATE => 250)
port map(rst_n_i => s_rst_n,
clk_i => clk_20MHz_i,
led_intensity_i => c_LED_INTENSITY,
led_state_i => f_STD_LOGIC_VECTOR(s_led_state_array),
column_o(0) => led_array_o.WR_OWNADDR_I2C,
column_o(1) => led_array_o.WR_GMT_TTL_TTLN,
column_o(2) => led_array_o.WR_LINK_SYSERROR,
column_o(3) => led_array_o.WR_OK_SYSPW,
column_o(4) => led_array_o.MULTICAST_2_0,
column_o(5) => led_array_o.MULTICAST_3_1,
line_o(0) => led_array_o.CTRL0,
line_o(1) => led_array_o.CTRL1,
line_oen_o(0) => led_array_o.CTRL0_OEN,
line_oen_o(1) => led_array_o.CTRL1_OEN);
inst_rtm_detector: rtm_detector
port map(RTMM_i => rtm_i.RTMM_N,
RTMP_i => rtm_i.RTMP_N,
ok_RTMM_o => s_ok_RTMM,
ok_RTMP_o => s_ok_RTMP);
end Behavioral;
hdl/IMAGES/image1/rtl/image1_led_pkg.vhd 0 → 100644
View file @ accb11b0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: image1_led_pkg.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- date: 23-01-2013
--
-- version: 1.0
--
-- description: Package for easy accessing LED array in CONV-TTL-BLO V2
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bicolor_led_ctrl_pkg.ALL;
package image1_led_pkg is
--! LEDs IP core constants
constant c_NB_COLUMN : NATURAL := 6;
constant c_NB_LINE : NATURAL := 2;
--! LEDs
constant c_NB_ARRAY_LEDS : NATURAL := 12;
constant c_LED_INTENSITY : STD_LOGIC_VECTOR(6 downto 0) := "0011111";
--! Front array LEDs individual assignment
--! Pairings:
--! COLUMN t_led_state
--! 0 0 - 6
--! 1 1 - 7
--! 2 2 - 8
--! 3 3 - 9
--! 4 4 - 10
--! 5 5 - 11
constant c_LED_NB_WR_ADDR : NATURAL := 0;
constant c_LED_NB_WR_GMT : NATURAL := 1;
constant c_LED_NB_WR_LINK : NATURAL := 2;
constant c_LED_NB_WR_OK : NATURAL := 3;
constant c_LED_NB_MULTICAST0 : NATURAL := 4;
constant c_LED_NB_MULTICAST1 : NATURAL := 5;
constant c_LED_NB_I2C : NATURAL := 6;
constant c_LED_NB_TTL_N : NATURAL := 7;
constant c_LED_NB_ERR : NATURAL := 8;
constant c_LED_NB_PWR : NATURAL := 9;
constant c_LED_NB_MULTICAST2 : NATURAL := 10;
constant c_LED_NB_MULTICAST3 : NATURAL := 11;
constant c_LED_COLOR_PWR : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_ERR : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_RED);
constant c_LED_COLOR_TTL_N : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_I2C : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_OK : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_LINK : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_GMT : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_ADDR : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST3 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST2 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST1 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST0 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
type t_leds_array_top is
record
PWR : STD_LOGIC;
ERR : STD_LOGIC;
TTL_N : STD_LOGIC;
I2C : STD_LOGIC;
end record;
type t_leds_array_middle is
record
WR_OK : STD_LOGIC;
WR_LINK : STD_LOGIC;
WR_GMT : STD_LOGIC;
WR_ADDR : STD_LOGIC;
end record;
type t_leds_array_bottom is
record
MULTICAST : UNSIGNED(3 downto 0);
end record;
type t_leds_array is
record
top : t_leds_array_top;
middle : t_leds_array_middle;
bottom : t_leds_array_bottom;
end record;
type t_led_state is
record
STATE : STD_LOGIC_VECTOR(1 downto 0);
end record;
type t_led_state_array is array(natural range <>) of t_led_state;
function f_LED_STATE(state: STD_LOGIC_VECTOR(1 downto 0)) return t_led_state;
function f_STD_LOGIC_VECTOR(led_state : t_led_state) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(led_state_array : t_led_state_array)
return STD_LOGIC_VECTOR;
end image1_led_pkg;
package body image1_led_pkg is
--! @brief Translation function from STD_LOGIC_VECTOR to t_led_state
--! @param state LED state in STD_LOGIC_VECTOR format
function f_LED_STATE(state: STD_LOGIC_VECTOR(1 downto 0)) return t_led_state is
variable v_return : t_led_state;
begin
v_return.STATE(0) := state(0);
v_return.STATE(1) := state(1);
return v_return;
end f_LED_STATE;
--! @brief Translation function from STD_LOGIC_VECTOR to
--! t_led_state
--! @param led_state_array LED state in STD_LOGIC_VECTOR format
function f_STD_LOGIC_VECTOR(led_state : t_led_state)
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(1 downto 0);
begin
v_return(0) := led_state.STATE(0);
v_return(1) := led_state.STATE(1);
return v_return;
end f_STD_LOGIC_VECTOR;
--! @brief Translation function from STD_LOGIC_VECTOR to
--! t_led_state_array
--! @param led_state_array LED array state in STD_LOGIC_VECTOR format
function f_STD_LOGIC_VECTOR(led_state_array : t_led_state_array)
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(2*c_NB_COLUMN*c_NB_LINE - 1 downto 0);
variable v_led_state_tmp : t_led_state;
variable v_led_state_slv_tmp : STD_LOGIC_VECTOR(1 downto 0);
begin
for i in 0 to (c_NB_COLUMN*c_NB_LINE - 1) loop
v_led_state_tmp := led_state_array(i);
v_led_state_slv_tmp := f_STD_LOGIC_VECTOR(v_led_state_tmp);
v_return(2*i + 1 downto 2*i) := v_led_state_slv_tmp;
end loop;
return v_return;
end f_STD_LOGIC_VECTOR;
end image1_led_pkg;
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ accb11b0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: image1_top.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- date: 23-01-2013
--
-- version: 1.0
--
-- description: Package for top entity of CONV-TTL-BLO V1
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library work;
......@@ -16,6 +49,8 @@ package image1_pkg is
--! Blocking repetition parameters
constant c_NUMBER_OF_CHANNELS : NATURAL := 6;
--! Pulse repetition constants
constant c_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
constant c_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns;
......@@ -52,9 +87,9 @@ package image1_pkg is
--! will be processed as an access to such register (indeed, like
--! accessing to byte 0).
--! ==================================
--! M25P32 [0200-03FF]
--! MULTIBOOT [0080-00CF]
--! I2C_SLAVE [0040-007F]
--! M25P32 [0200-03FF]
--! MULTIBOOT [0080-00CF]
--! I2C_SLAVE [0040-007F]
--! ==================================
constant c_ADDR_M25P32 : t_wishbone_address := X"00000200";
constant c_ADDR_MULTIBOOT : t_wishbone_address := X"00000080";
......@@ -215,7 +250,7 @@ package image1_pkg is
end component;
-- function check_sys_cfg return BOOLEAN;
-- function check_sys_cfg return BOOLEAN;
function f_RENESAS_I2C_ADDRESSING(VME_slot : UNSIGNED(4 downto 0))
return STD_LOGIC_VECTOR;
end image1_pkg;
......@@ -236,6 +271,7 @@ package body image1_pkg is
-- return TRUE;
-- end check_sys_cfg;
--! @brief Translation function for i2c_addressing
--! The specification of this criteria can be found in
--! Samuel's document "Specification. Access to board data
......
hdl/IMAGES/image1/rtl/image1_wrappers_pkg.vhd 0 → 100644
View file @ accb11b0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: image1_wrappers_pkg.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- date: 23-01-2013
--
-- version: 1.0
--
-- description: Package for the wrappers used in image1_core.vhd of
-- CONV-TTL-BLO V2
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
package image1_wrappers_pkg is
--! Wrappers for image1_top FPGA pinouts
type t_led_array_o is
record
CTRL0 : STD_LOGIC;
CTRL0_OEN : STD_LOGIC;
CTRL1 : STD_LOGIC;
CTRL1_OEN : STD_LOGIC;
MULTICAST_2_0 : STD_LOGIC;
MULTICAST_3_1 : STD_LOGIC;
WR_GMT_TTL_TTLN : STD_LOGIC;
WR_LINK_SYSERROR : STD_LOGIC;
WR_OK_SYSPW : STD_LOGIC;
WR_OWNADDR_I2C : STD_LOGIC;
end record;
type t_i2c_slave_i is
record
SCL_I : STD_LOGIC;
SDA_I : STD_LOGIC;
end record;
type t_i2c_slave_o is
record
SCL_O : STD_LOGIC;
SCL_OE : STD_LOGIC;
SDA_O : STD_LOGIC;
SDA_OE : STD_LOGIC;
end record;
type t_spi_master_i is
record
DIN : STD_LOGIC;
end record;
type t_spi_master_o is
record
CCLK : STD_LOGIC;
CSO_B_N : STD_LOGIC;
MOSI : STD_LOGIC;
end record;
type t_rtm_i is
record
RTMM_N : STD_LOGIC_VECTOR(2 downto 0);
RTMP_N : STD_LOGIC_VECTOR(2 downto 0);
end record;
constant c_led_array_default : t_led_array_o := (CTRL0 => '0',
CTRL0_OEN => '0',
CTRL1 => '0',
CTRL1_OEN => '0',
MULTICAST_2_0 => '0',
MULTICAST_3_1 => '0',
WR_GMT_TTL_TTLN => '0',
WR_LINK_SYSERROR => '0',
WR_OK_SYSPW => '0',
WR_OWNADDR_I2C => '0');
end image1_wrappers_pkg;
package body image1_wrappers_pkg is
end image1_wrappers_pkg;
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ accb11b0
......@@ -8,6 +8,8 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALl;
use std.textio.ALL;
use work.image1_pkg.ALL;
use work.image1_led_pkg.ALL;
use work.image1_wrappers_pkg.ALL;
use work.image1_top_tb_pkg.ALL;
use work.i2c_tb_pkg.ALL;
use work.i2c_slave_pkg.ALL;
......@@ -18,14 +20,16 @@ end image1_top_tb;
architecture behavior of image1_top_tb is
constant c_CLK20M : TIME := 50 ns;
--! ========================================================================
--! Signals for the image1_top module
--! ========================================================================
signal s_RST_N : STD_LOGIC := '1'; --! Never active
signal s_CLK20_VCXO : STD_LOGIC := '0';
signal s_FPGA_CLK_P : STD_LOGIC := '1';
signal s_FPGA_CLK_N : STD_LOGIC := '0';
signal s_led_pw_o : STD_LOGIC;
signal s_led_err_o : STD_LOGIC;
signal s_led_ttl_o : STD_LOGIC;
--! LEDs
signal s_led_array_o : t_led_array_o; -- STATUS LEDs
signal s_pulse_led : t_pulse_led_vector;
signal s_pulse_i : t_pulse_vector;
signal s_pulse_o : t_pulse_vector;
......@@ -45,13 +49,9 @@ architecture behavior of image1_top_tb is
signal s_SPI_master_o : t_SPI_master_out;
signal s_SPI_slave_i : t_SPI_slave_in;
signal s_SPI_slave_o : t_SPI_slave_out;
--! This LED will show the status of the PLL
signal s_led_link_up_o : STD_LOGIC;
signal s_led_pps_o : STD_LOGIC;
signal s_led_wr_ok_o : STD_LOGIC;
signal s_fpga_en : t_fpga_en;
signal level : STD_LOGIC := '1';
signal switch_i : STD_LOGIC;
signal switch_i : STD_LOGIC_VECTOR(1 downto 1);
signal manual_rst_n_o : STD_LOGIC;
signal s_RTM_id_i : t_RTM_id := c_RTM_id_default;
......@@ -85,6 +85,7 @@ architecture behavior of image1_top_tb is
signal s_wr_fw_regs : t_wr_fw_reg;
signal s_wr_fw_regs_slv : t_wr_fw_reg_slv;
signal s_test : STD_LOGIC;
begin
s_MULTIBOOT_regs_slv <= f_STD_LOGIC_VECTOR(s_MULTIBOOT_regs);
......@@ -100,6 +101,14 @@ begin
s_rst <= s_rst_SYS_A(c_RST_A_CLKS - 1);
--! Clock process definitions
p_CLK20_VCXO :process
begin
s_CLK20_VCXO <= not(s_CLK20_VCXO);
wait for c_CLK20M/2;
end process;
--! Clock process definitions
p_FPGA_CLK :process
begin
......@@ -108,41 +117,43 @@ begin
wait for c_PLL_IN_PERIOD/2;
end process;
--! @brief Process to bypass internal signals requiered for correct
--! use of i2c_master_driver
p_sig_spy : process is
begin
init_signal_spy("/uut/s_clk.SYS_A", "wb_clk", 1);
init_signal_spy("/uut/s_rst.SYS_A", "s_rst_SYS_A", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_regs/s_CTR0",
init_signal_spy("/uut/s_clk_125MHz", "s_test", 1);
init_signal_spy("/uut/inst_image1_core/s_clk.SYS_A", "wb_clk", 1);
init_signal_spy("/uut/inst_image1_core/s_rst.SYS_A", "s_rst_SYS_A", 1);
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_regs/s_CTR0",
"s_I2C_regs.CTR0", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_regs/s_LT",
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_regs/s_LT",
"s_I2C_regs.LT", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_slave_core/s_DRXA_slv",
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRXA_slv",
"s_I2C_regs.DRXA", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_slave_core/s_DRXB_slv",
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRXB_slv",
"s_I2C_regs.DRXB", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_slave_regs/s_DTX",
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_regs/s_DTX",
"s_I2C_regs.DTX", 1);
init_signal_spy("/uut/inst_multiboot/multiboot_regs_inst/s_CTR0",
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_CTR0",
"s_MULTIBOOT_regs.CTR0", 1);
init_signal_spy("/uut/inst_multiboot/multiboot_regs_inst/s_CTR1",
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_CTR1",
"s_MULTIBOOT_regs.CTR1", 1);
init_signal_spy("/uut/inst_multiboot/multiboot_regs_inst/s_STAT",
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_STAT",
"s_MULTIBOOT_regs.STAT", 1);
init_signal_spy("/uut/inst_multiboot/multiboot_regs_inst/s_MBA",
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_MBA",
"s_MULTIBOOT_regs.MBA", 1);
init_signal_spy("/uut/inst_multiboot/multiboot_regs_inst/s_GBA",
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_GBA",
"s_MULTIBOOT_regs.GBA", 1);
init_signal_spy("/uut/inst_multiboot/multiboot_regs_inst/s_MBA",
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_MBA",
"s_MULTIBOOT_regs.MBA", 1);
init_signal_spy("/uut/inst_multiboot/multiboot_regs_inst/s_GBA_ICAP",
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_GBA_ICAP",
"s_MULTIBOOT_regs.GBA_ICAP", 1);
init_signal_spy("/uut/inst_multiboot/multiboot_regs_inst/s_MBA_ICAP",
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_MBA_ICAP",
"s_MULTIBOOT_regs.MBA_ICAP", 1);
init_signal_spy("/uut/inst_m25p32/inst_m25p32_regs/s_FMI",
init_signal_spy("/uut/inst_image1_core/inst_m25p32/inst_m25p32_regs/s_FMI",
"s_M25P32_regs.FMI", 1);
init_signal_spy("/uut/inst_m25p32/inst_m25p32_regs/s_SR_m25p32",
init_signal_spy("/uut/inst_image1_core/inst_m25p32/inst_m25p32_regs/s_SR_m25p32",
"s_M25P32_regs.SR_m25p32", 1);
wait;
end process p_sig_spy;
......@@ -175,43 +186,49 @@ begin
uut: image1_top
generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
port map(FPGA_CLK_P => s_FPGA_CLK_P,
FPGA_CLK_N => s_FPGA_CLK_N,
led_pw_o => s_led_pw_o ,
led_err_o => s_led_err_o,
led_ttl_o => s_led_ttl_o,
led_o_front => s_pulse_led.FRONT,
led_o_rear => s_pulse_led.REAR,
pulse_i_front => s_pulse_i.FRONT,
pulse_o_front => s_pulse_o.FRONT,
pulse_i_rear => s_pulse_i.REAR,
pulse_o_rear => s_pulse_o.REAR,
inv_i => s_inv_i,
inv_o => s_inv_o,
SCL_I => s_I2C_master_o.SCL,
SCL_O => open,
SCL_OE => s_scl_slave_oen,
SDA_I => s_I2C_slave_i.SDA,
SDA_O => s_I2C_slave_o.SDA,
SDA_OE => s_sda_slave_oen,
FPGA_GA => s_FPGA_GA,
FPGA_GAP => s_FPGA_GAP,
FPGA_PROM_CCLK => s_SPI_master_o.CCLK,
FPGA_PROM_CSO_B_N => s_SPI_master_o.CSO_B_N,
FPGA_PROM_DIN => s_SPI_master_i.DIN,
FPGA_PROM_MOSI => s_SPI_master_o.MOSI,
led_link_up_o => s_led_link_up_o,
led_pps_o => s_led_pps_o,
led_wr_ok_o => s_led_wr_ok_o,
fpga_o_en => s_fpga_en.GEN,
fpga_o_blo_en => s_fpga_en.BLO,
fpga_o_ttl_en => s_fpga_en.TTL,
fpga_o_inv_en => s_fpga_en.INV,
level => level,
switch_i => switch_i,
manual_rst_n_o => manual_rst_n_o,
FPGA_RTMM => s_RTM_id_i.RTMM,
FPGA_RTMP => s_RTM_id_i.RTMP);
port map(RST_N => s_RST_N,
CLK20_VCXO => s_CLK20_VCXO,
FPGA_CLK_P => s_FPGA_CLK_P,
FPGA_CLK_N => s_FPGA_CLK_N,
LED_CTRL0 => s_led_array_o.CTRL0,
LED_CTRL0_OEN => s_led_array_o.CTRL0_OEN,
LED_CTRL1 => s_led_array_o.CTRL1,
LED_CTRL1_OEN => s_led_array_o.CTRL1_OEN,
LED_MULTICAST_2_0 => s_led_array_o.MULTICAST_2_0,
LED_MULTICAST_3_1 => s_led_array_o.MULTICAST_3_1,
LED_WR_GMT_TTL_TTLN => s_led_array_o.WR_GMT_TTL_TTLN,
LED_WR_LINK_SYSERROR => s_led_array_o.WR_LINK_SYSERROR,
LED_WR_OK_SYSPW => s_led_array_o.WR_OK_SYSPW,
LED_WR_OWNADDR_I2C => s_led_array_o.WR_OWNADDR_I2C,
PULSE_FRONT_LED_N => s_pulse_led.FRONT,
PULSE_REAR_LED_N => s_pulse_led.REAR,
FPGA_INPUT_TTL_N => s_pulse_i.FRONT,
FPGA_OUT_TTL => s_pulse_o.FRONT,
FPGA_BLO_IN => s_pulse_i.REAR,
FPGA_TRIG_BLO => s_pulse_o.REAR,
INV_IN_N => s_inv_i,
INV_OUT => s_inv_o,
SCL_I => s_I2C_master_o.SCL,
SCL_O => open,
SCL_OE => s_scl_slave_oen,
SDA_I => s_I2C_slave_i.SDA,
SDA_O => s_I2C_slave_o.SDA,
SDA_OE => s_sda_slave_oen,
FPGA_GA => s_FPGA_GA,
FPGA_GAP => s_FPGA_GAP,
FPGA_PROM_CCLK => s_SPI_master_o.CCLK,
FPGA_PROM_CSO_B_N => s_SPI_master_o.CSO_B_N,
FPGA_PROM_DIN => s_SPI_master_i.DIN,
FPGA_PROM_MOSI => s_SPI_master_o.MOSI,
FPGA_OE => s_fpga_en.GEN,
FPGA_BLO_OE => s_fpga_en.BLO,
FPGA_TRIG_TTL_OE => s_fpga_en.TTL,
FPGA_INV_OE => s_fpga_en.INV,
LEVEL => level,
EXTRA_SWITCH => switch_i,
MR_N => manual_rst_n_o,
FPGA_RTMM_N => s_RTM_id_i.RTMM,
FPGA_RTMP_N => s_RTM_id_i.RTMP);
--! Stimulus process
......
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ accb11b0
......@@ -21,50 +21,57 @@ package image1_top_tb_pkg is
component image1_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (FPGA_CLK_P : in STD_LOGIC;
FPGA_CLK_N : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
port (RST_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
FPGA_CLK_N : in STD_LOGIC;
--! LEDs
LED_CTRL0 : out STD_LOGIC;
LED_CTRL0_OEN : out STD_LOGIC;
LED_CTRL1 : out STD_LOGIC;
LED_CTRL1_OEN : out STD_LOGIC;
LED_MULTICAST_2_0 : out STD_LOGIC;
LED_MULTICAST_3_1 : out STD_LOGIC;
LED_WR_GMT_TTL_TTLN : out STD_LOGIC;
LED_WR_LINK_SYSERROR : out STD_LOGIC;
LED_WR_OK_SYSPW : out STD_LOGIC;
LED_WR_OWNADDR_I2C : out STD_LOGIC;
--! I/Os for pulses
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP : in STD_LOGIC_VECTOR(2 downto 0));
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
FPGA_OE : out STD_LOGIC;
FPGA_BLO_OE : out STD_LOGIC;
FPGA_TRIG_TTL_OE : out STD_LOGIC;
FPGA_INV_OE : out STD_LOGIC;
LEVEL : in STD_LOGIC;
EXTRA_SWITCH : in STD_LOGIC_VECTOR(1 downto 1);--! General enable
MR_N : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0));
end component;
type t_pulse_vector is
......
hdl/IMAGES/image1/top/image1_top.vhd 0 → 100644
View file @ accb11b0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO V1
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: image1_top.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
--
-- date: 01-12-2012
--
-- version: 0.9
--
-- description: Top entity of CONV-TTL-BLO V1
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library IEEE;
library unisim;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.image1_pkg.ALL;
use work.image1_wrappers_pkg.ALL;
use work.wishbone_pkg.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity image1_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (RST_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
FPGA_CLK_N : in STD_LOGIC;
--! LEDs
LED_CTRL0 : out STD_LOGIC;
LED_CTRL0_OEN : out STD_LOGIC;
LED_CTRL1 : out STD_LOGIC;
LED_CTRL1_OEN : out STD_LOGIC;
LED_MULTICAST_2_0 : out STD_LOGIC;
LED_MULTICAST_3_1 : out STD_LOGIC;
LED_WR_GMT_TTL_TTLN : out STD_LOGIC;
LED_WR_LINK_SYSERROR : out STD_LOGIC;
LED_WR_OK_SYSPW : out STD_LOGIC;
LED_WR_OWNADDR_I2C : out STD_LOGIC;
--! I/Os for pulses
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
FPGA_OE : out STD_LOGIC;
FPGA_BLO_OE : out STD_LOGIC;
FPGA_TRIG_TTL_OE : out STD_LOGIC;
FPGA_INV_OE : out STD_LOGIC;
LEVEL : in STD_LOGIC;--!TTL/INV_TTL_N
EXTRA_SWITCH : in STD_LOGIC_VECTOR(1 downto 1);--! General enable
MR_N : out STD_LOGIC;--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0));
end image1_top;
architecture Behavioral of image1_top is
component image1_core is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (rst_n : in STD_LOGIC;
clk_20MHz_i : in STD_LOGIC;
clk_125MHz_i : in STD_LOGIC;
--! LEDs
led_array_o : out t_led_array_o;
--! I/Os for pulses
led_front_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front_n : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i_n : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
i2c_slave_i : in t_i2c_slave_i;
i2c_slave_o : out t_i2c_slave_o;
--! FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
spi_master_i : in t_spi_master_i;
spi_master_o : out t_spi_master_o;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
rtm_i : in t_rtm_i);
end component;
signal s_clk_125MHz : STD_LOGIC;
signal s_led_array : t_led_array_o := c_led_array_default;
signal s_i2c_slave_i : t_i2c_slave_i;
signal s_i2c_slave_o : t_i2c_slave_o;
signal s_spi_master_i : t_spi_master_i;
signal s_spi_master_o : t_spi_master_o;
signal s_rtm_i : t_rtm_i;
signal s_switch_i : STD_LOGIC_VECTOR(1 downto 1);
begin
inst_125m_IBUFGDS : IBUFGDS
generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => TRUE)
port map (O => s_clk_125MHz, I => FPGA_CLK_P,
IB => FPGA_CLK_N);
LED_CTRL0 <= s_led_array.CTRL0;
LED_CTRL0_OEN <= s_led_array.CTRL0_OEN;
LED_CTRL1 <= s_led_array.CTRL1;
LED_CTRL1_OEN <= s_led_array.CTRL1_OEN;
LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0;
LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1;
LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN;
LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR;
LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW;
LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C;
s_i2c_slave_i.SCL_I <= SCL_I;
s_i2c_slave_i.SDA_I <= SDA_I;
SCL_O <= s_i2c_slave_o.SCL_O;
SCL_OE <= s_i2c_slave_o.SCL_OE;
SDA_O <= s_i2c_slave_o.SDA_O;
SDA_OE <= s_i2c_slave_o.SDA_OE;
s_spi_master_i.DIN <= FPGA_PROM_DIN;
FPGA_PROM_CCLK <= s_spi_master_o.CCLK;
FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N;
FPGA_PROM_MOSI <= s_spi_master_o.MOSI;
s_rtm_i.RTMM_N <= FPGA_RTMM_N;
s_rtm_i.RTMP_N <= fpga_rtmp_n;
s_switch_i <= EXTRA_SWITCH;
inst_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6)
port map(rst_n => RST_N,
clk_20MHz_i => CLK20_VCXO,
clk_125MHz_i => s_clk_125MHz,
led_array_o => s_led_array,
led_front_n => PULSE_FRONT_LED_N,
led_rear_n => PULSE_REAR_LED_N,
pulse_i_front_n => FPGA_INPUT_TTL_N,
pulse_o_front => FPGA_OUT_TTL,
pulse_i_rear => FPGA_BLO_IN,
pulse_o_rear => FPGA_TRIG_BLO,
inv_i_n => INV_IN_N,
inv_o => INV_OUT,
i2c_slave_i => s_i2c_slave_i,
i2c_slave_o => s_i2c_slave_o,
FPGA_GA => FPGA_GA ,
FPGA_GAP => FPGA_GAP,
spi_master_i => s_spi_master_i,
spi_master_o => s_spi_master_o,
fpga_o_en => FPGA_OE,
fpga_o_blo_en => FPGA_BLO_OE,
fpga_o_ttl_en => FPGA_TRIG_TTL_OE,
fpga_o_inv_en => FPGA_INV_OE,
level => LEVEL,
switch_i => s_switch_i(1),
manual_rst_n_o => MR_N,
rtm_i => s_rtm_i);
end Behavioral;
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