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C
Conv TTL Blocking
Commit b82474c4 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Uploading UG files (unfinished)

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doc/.gitignore
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ug/
ug/userGuide.pdf
old-ug-conv-ttl-blo.pdf
userGuide.pdf
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doc/ug/ug-conv-ttl-blo.tex
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......@@ -491,7 +491,23 @@ the pulse signals are controlled mainly by the resistors at the gate of the MOSF
% SEC: FPGA Logic
%======================================================================================
\section{FPGA Logic}
\label{sec:fpga-logic}
\label{sec:fpga}
\subsection{Block diagram}
\label{sec:fpga-bd}
A block diagram of the FPGA design is presented in Fig.~\ref{fig:fpga-bd}.
\begin{figure}
\begin{center}
\includegraphics[width=\textwidth]{Figures/fpga-bd}
\caption{Block diagram of FPGA logic design}
\label{fig:fpga-bd}
\end{center}
\end{figure}
\textcolor{red}{\textbf{details about logic}}
\textcolor{red}{\textbf{pulse generator}}
%======================================================================================
......
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