Skip to content

C
Conv TTL Blocking
Commit bf36af66 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

Continuing work on ug-conv-ttl-blo

parent 1edb77ce
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1936 additions and 246 deletions
doc/ug/fig/front-panel.svg
View file @ bf36af66
This diff is collapsed.
doc/ug/fig/ttl-chan.svg 0 → 100644
View file @ bf36af66
This source diff could not be displayed because it is too large. You can view the blob instead.
doc/ug/ug-conv-ttl-blo.tex
View file @ bf36af66
This diff is collapsed.
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ bf36af66
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1370609192">
<transform xil_pn:end_ts="1370850931" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1370850931">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1370609192">
<transform xil_pn:end_ts="1370850931" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1370850931">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1370609192">
<transform xil_pn:end_ts="1370850931" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1370850931">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1370609192">
<transform xil_pn:end_ts="1370850931" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1370850931">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1370609192">
<transform xil_pn:end_ts="1370850931" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1370850931">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1370609192">
<transform xil_pn:end_ts="1370850931" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1370850931">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1370609192">
<transform xil_pn:end_ts="1370850931" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1370850931">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370609208" xil_pn:in_ck="-4867058225791759267" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1370609192">
<transform xil_pn:end_ts="1370850949" xil_pn:in_ck="-4867058225791759267" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1370850931">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1370609208" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1370609208">
<transform xil_pn:end_ts="1370850949" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1370850949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370609217" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1370609208">
<transform xil_pn:end_ts="1370850958" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1370850949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1370609256" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1370609217">
<transform xil_pn:end_ts="1370850995" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1370850958">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1370609294" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1370609256">
<transform xil_pn:end_ts="1370851034" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1370850995">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1370609316" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1370609294">
<transform xil_pn:end_ts="1370851055" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1370851034">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -170,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1370609294" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1370609283">
<transform xil_pn:end_ts="1370851034" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1370851023">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ bf36af66
......@@ -105,6 +105,10 @@ end conv_ttl_blo_v2;
architecture behav of conv_ttl_blo_v2 is
--============================================================================
-- Type declarations
--============================================================================
type t_ttlbar_nosig_cnt is array (1 to g_nr_ttl_chan) of unsigned(13 downto 0);
--============================================================================
-- Constant declarations
......@@ -308,6 +312,11 @@ architecture behav of conv_ttl_blo_v2 is
signal trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_inv : std_logic_vector(g_nr_inv_chan downto 1);
signal trig_ttl, trig_blo : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_ttl_mux : std_logic_vector(g_nr_ttl_chan downto 1);
-- TTL-BAR lack of signal counter
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
signal ttlbar_nosig : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for blocking and TTL pulse outputs
signal pulse_outputs : std_logic_vector(g_nr_ttl_chan downto 1);
......@@ -553,12 +562,33 @@ begin
--============================================================================
-- TTL and blocking pulse generation logic
--============================================================================
trig_ttl <= not fpga_input_ttl_n_i when (ttl_switch_n_i = '0') else
fpga_input_ttl_n_i;
-- First, the TTL signal mux, selected via the TTL switch
trig_ttl_mux <= not fpga_input_ttl_n_i when (ttl_switch_n_i = '0') else
fpga_input_ttl_n_i;
-- Now we assign the trigger signals
trig_ttl <= trig_ttl_mux and (not ttlbar_nosig);
trig_blo <= fpga_blo_in_i;
trig <= trig_ttl or trig_blo;
gen_ttl_pulse_generators: for i in 1 to g_nr_ttl_chan generate
-- Process to detect lack of signal on TTL line
p_ttlbar_nosig : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') or (trig_ttl_mux(i) = '0') then
ttlbar_nosig(i) <= '0';
ttlbar_nosig_cnt(i) <= (others => '0');
elsif (trig_ttl_mux(i) = '1') then
ttlbar_nosig_cnt(i) <= ttlbar_nosig_cnt(i) + 1;
if (ttlbar_nosig_cnt(i) = 12499) then
ttlbar_nosig(i) <= '1';
ttlbar_nosig_cnt(i) <= (others => '0');
end if;
end if;
end if;
end process p_ttlbar_nosig;
-- Output pulse generators
cmp_ttl_pulse_gen : ctb_pulse_gen
generic map
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment