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c06b7459
Commit
c06b7459
authored
Oct 10, 2013
by
Theodor-Adrian Stana
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Plain Diff
Changed writereg and readreg command and added writemregs
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
b3901f52
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
38 additions
and
26 deletions
+38
-26
multiboot.py
test/multiboot/multiboot.py
+16
-19
vbcp.py
test/vbcp/vbcp.py
+22
-7
No files found.
test/multiboot/multiboot.py
View file @
c06b7459
...
...
@@ -42,21 +42,14 @@ def spi_transfer(cs, dat):
retval
=
0
wval
=
[]
if
isinstance
(
dat
,
int
):
wval
.
append
(
dat
)
wval
.
append
((
cs
<<
2
)
|
1
)
wval
.
append
(
0
)
wval
.
append
(
0
)
ctb
.
write
(
0x90
,
(((
cs
<<
10
)
|
0x100
)
|
dat
))
else
:
for
i
in
xrange
(
len
(
dat
)):
wval
.
append
(
dat
[
i
])
wval
.
append
((
cs
<<
2
)
|
1
)
wval
.
append
(
0
)
wval
.
append
(
0
)
ctb
.
write
(
0x90
,
wval
)
wval
.
append
((((
cs
<<
10
)
|
0x100
)
|
dat
[
i
]))
ctb
.
writemregs
(
0x90
,
wval
)
while
(
retval
&
(
1
<<
9
)
==
0
):
retval
=
ctb
.
read
(
0x90
)
return
retval
&
0xFF
# ctb.write(0x90, [(((cs << 10) | 0x100) | d) for d in dat])
# while (retval & (1 << 9) == 0):
# retval = ctb.read(0x90)
# return retval & 0xFF
...
...
@@ -65,10 +58,9 @@ def flash_write(addr, dat):
spi_transfer
(
0
,
0
)
spi_transfer
(
1
,
0x06
)
spi_transfer
(
0
,
0
)
spi_transfer
(
1
,[
0x02
,(
addr
&
0xFF0000
)
>>
16
])
spi_transfer
(
1
,[(
addr
&
0xFF00
)
>>
8
,
(
addr
&
0xFF
)])
for
i
in
xrange
(
0
,
len
(
dat
),
2
):
spi_transfer
(
1
,[
dat
[
i
],
dat
[
i
+
1
]])
spi_transfer
(
1
,[
0x02
,(
addr
&
0xFF0000
)
>>
16
,(
addr
&
0xFF00
)
>>
8
,
(
addr
&
0xFF
)])
for
i
in
xrange
(
0
,
len
(
dat
),
4
):
spi_transfer
(
1
,[
dat
[
i
],
dat
[
i
+
1
],
dat
[
i
+
2
],
dat
[
i
+
3
]])
spi_transfer
(
0
,
0
)
# spi_transfer(0,0)
# spi_transfer(1,0x06)
...
...
@@ -88,8 +80,7 @@ def flash_read(addr, nrbytes):
#spi_transfer(1,(addr & 0xFF0000) >> 16)
#spi_transfer(1,(addr & 0xFF00) >> 8)
#spi_transfer(1,(addr & 0xFF))
spi_transfer
(
1
,[
0x0b
,
(
addr
&
0xFF0000
)
>>
16
])
spi_transfer
(
1
,[(
addr
&
0xFF00
)
>>
8
,
(
addr
&
0xFF
)])
spi_transfer
(
1
,[
0x0b
,
(
addr
&
0xFF0000
)
>>
16
,(
addr
&
0xFF00
)
>>
8
,
(
addr
&
0xFF
)])
spi_transfer
(
1
,
0
)
for
i
in
range
(
nrbytes
):
ret
.
append
(
spi_transfer
(
1
,
0
))
...
...
@@ -104,8 +95,7 @@ def flash_serase(addr):
#spi_transfer(1,(addr & 0xFF0000) >> 16)
#spi_transfer(1,(addr & 0xFF00) >> 8)
#spi_transfer(1,(addr & 0xFF))
spi_transfer
(
1
,[
0xd8
,
(
addr
&
0xFF0000
)
>>
16
])
spi_transfer
(
1
,[(
addr
&
0xFF00
)
>>
8
,
(
addr
&
0xFF
)])
spi_transfer
(
1
,[
0xd8
,
(
addr
&
0xFF0000
)
>>
16
,(
addr
&
0xFF00
)
>>
8
,
(
addr
&
0xFF
)])
spi_transfer
(
0
,
0
)
def
flash_berase
():
...
...
@@ -190,13 +180,14 @@ if __name__ == "__main__":
print
"WRITE"
f
=
open
(
"conv.txt"
,
'r'
)
addr
=
0
tdat
=
[]
twr
=
[]
twa
=
[]
te
=
[]
f
=
open
(
"conv.txt"
,
'r'
)
for
fdata
in
f
:
print
addr
data
=
[]
...
...
@@ -208,6 +199,9 @@ if __name__ == "__main__":
pass
te2
=
time
.
time
()
te
.
append
(
te2
-
te1
)
#rd = flash_read(0x000100,256)
#rd = "".join(["0x%02X " % b for b in rd])
#print rd
try
:
t1
=
time
.
time
()
for
i
in
xrange
(
256
):
...
...
@@ -229,6 +223,9 @@ if __name__ == "__main__":
twr
.
append
(
t4
-
t3
)
twa
.
append
(
t5
-
t4
)
#if (addr == 0x10000):
# break
#print data
#print len(data)
...
...
test/vbcp/vbcp.py
View file @
c06b7459
...
...
@@ -74,21 +74,36 @@ class VBCP:
def
close_conn
(
self
):
self
.
handle
.
close
()
def
write
(
self
,
addr
,
val
):
def
write
mregs
(
self
,
addr
,
val
):
self
.
write_cnt
+=
1
reg
=
addr
/
4
+
1
sl
=
(
0x40
|
((
~
self
.
slot
)
&
0x1f
))
<<
1
#reg = addr/4 + 1
#print '%02x' % sl
cmd
=
"iic4wr
%
x
%
x
%
x
%
s
\r\n
"
%
(
sl
,
(
addr
&
0xff00
)
>>
8
,
addr
&
0xff
,
' '
.
join
(
format
(
b
,
'x'
)
for
b
in
val
))
cmd
=
"writemregs
%
d
%
x
%
s
\r\n
"
%
(
self
.
slot
,
addr
,
' '
.
join
(
format
(
b
,
'x'
)
for
b
in
val
))
#print cmd
self
.
handle
.
send
(
cmd
)
_strip_resp
(
self
.
handle
.
recv
(
30
))
def
readmregs
(
self
,
addr
,
nrregs
):
self
.
read_cnt
+=
1
#reg = addr/4 + 1
cmd
=
"readmregs
%
d
%
x
%
d
\r\n
"
%
(
self
.
slot
,
addr
,
nrregs
)
self
.
handle
.
send
(
cmd
)
resp
=
_strip_resp
(
self
.
handle
.
recv
(
30
))
return
resp
def
write
(
self
,
addr
,
val
):
self
.
write_cnt
+=
1
#reg = addr/4 + 1
cmd
=
"writereg
%
d
%
x
%
x
\r\n
"
%
(
self
.
slot
,
addr
,
val
)
#print cmd
#cmd = "writereg %d %d %x\r\n" % (self.slot, reg, val)
self
.
handle
.
send
(
cmd
)
_strip_resp
(
self
.
handle
.
recv
(
30
))
def
read
(
self
,
addr
):
self
.
read_cnt
+=
1
reg
=
addr
/
4
+
1
cmd
=
"readreg
%
d
%
d
\r\n
"
%
(
self
.
slot
,
reg
)
#reg = addr/4 + 1
cmd
=
"readreg
%
d
%
x
\r\n
"
%
(
self
.
slot
,
addr
)
#print cmd
self
.
handle
.
send
(
cmd
)
resp
=
_strip_resp
(
self
.
handle
.
recv
(
30
))
return
resp
...
...
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