Commit c4f77a46 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Add PTS firmware documentation

PDF files for the schematic and BOM for the RTM Tester Board are
also added.

old_rep_test/ folder is not pulse_gen/
parent b3d8cf93
build/
fig/
*.tex
*.bib
FILE=pts_hdlguide
all:
pdflatex -synctex=1 -interaction=nonstopmode *.tex
bibtex *.aux
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode *.tex
evince $(FILE).pdf &
clean:
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for PTS registers
-- Title : Wishbone slave core for PTS control and status registers
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Mon Apr 15 10:57:27 2013
-- Created : Tue Apr 30 11:25:57 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
......@@ -27,10 +27,12 @@ entity pts_regs is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'current test' in reg: 'control register'
pts_ctrl_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for BIT field: 'reset' in reg: 'control register'
pts_ctrl_rst_o : out std_logic;
-- Port for std_logic_vector field: 'current test' in reg: 'control and status register'
pts_csr_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for BIT field: 'reset' in reg: 'control and status register'
pts_csr_rst_o : out std_logic;
-- Port for std_logic_vector field: 'RTM' in reg: 'control and status register'
pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID'
pts_id_bits_o : out std_logic_vector(31 downto 0)
);
......@@ -38,8 +40,8 @@ end pts_regs;
architecture syn of pts_regs is
signal pts_ctrl_crrt_test_int : std_logic_vector(3 downto 0);
signal pts_ctrl_rst_int : std_logic ;
signal pts_csr_crrt_test_int : std_logic_vector(3 downto 0);
signal pts_csr_rst_int : std_logic ;
signal pts_id_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
......@@ -68,8 +70,8 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pts_ctrl_crrt_test_int <= "0000";
pts_ctrl_rst_int <= '0';
pts_csr_crrt_test_int <= "0000";
pts_csr_rst_int <= '0';
pts_id_bits_int <= x"424C4F32";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -85,11 +87,12 @@ begin
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
pts_ctrl_crrt_test_int <= wrdata_reg(3 downto 0);
pts_ctrl_rst_int <= wrdata_reg(31);
pts_csr_crrt_test_int <= wrdata_reg(3 downto 0);
pts_csr_rst_int <= wrdata_reg(15);
end if;
rddata_reg(3 downto 0) <= pts_ctrl_crrt_test_int;
rddata_reg(31) <= pts_ctrl_rst_int;
rddata_reg(3 downto 0) <= pts_csr_crrt_test_int;
rddata_reg(15) <= pts_csr_rst_int;
rddata_reg(21 downto 16) <= pts_csr_rtm_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
......@@ -101,13 +104,6 @@ begin
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
......@@ -117,6 +113,7 @@ begin
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
......@@ -140,9 +137,10 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- current test
pts_ctrl_crrt_test_o <= pts_ctrl_crrt_test_int;
pts_csr_crrt_test_o <= pts_csr_crrt_test_int;
-- reset
pts_ctrl_rst_o <= pts_ctrl_rst_int;
pts_csr_rst_o <= pts_csr_rst_int;
-- RTM
-- bits
pts_id_bits_o <= pts_id_bits_int;
rwaddr_reg <= wb_adr_i;
......
peripheral {
name = "PTS registers";
name = "PTS control and status registers";
description = "Registers of the PTS firmware";
hdl_entity = "pts_regs";
prefix = "pts";
reg {
name = "control register";
prefix = "ctrl";
name = "control and status register";
prefix = "csr";
field {
name = "current test";
prefix = "crrt_test";
......@@ -19,10 +19,19 @@ peripheral {
name = "reset";
prefix = "rst";
type = BIT;
align = 31;
align = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "RTM";
prefix = "rtm";
type = SLV;
align = 16;
size = 6;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pulse_cnt_wb.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_wb.wb
-- Created : Thu Apr 18 18:16:52 2013
-- Created : Tue Apr 30 08:48:19 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_wb.wb
......@@ -66,7 +66,31 @@ entity pulse_cnt_wb is
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH10 output'
pulse_cnt_ch10o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH10 input'
pulse_cnt_ch10i_val_i : in std_logic_vector(31 downto 0)
pulse_cnt_ch10i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH11 output'
pulse_cnt_ch11o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH11 input'
pulse_cnt_ch11i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH12 output'
pulse_cnt_ch12o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH12 input'
pulse_cnt_ch12i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH13 output'
pulse_cnt_ch13o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH13 input'
pulse_cnt_ch13i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH14 output'
pulse_cnt_ch14o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH14 input'
pulse_cnt_ch14i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH15 output'
pulse_cnt_ch15o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH15 input'
pulse_cnt_ch15i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH16 output'
pulse_cnt_ch16o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH16 input'
pulse_cnt_ch16i_val_i : in std_logic_vector(31 downto 0)
);
end pulse_cnt_wb;
......@@ -231,6 +255,78 @@ begin
rddata_reg(31 downto 0) <= pulse_cnt_ch10i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch11o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch11i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch12o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch12i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch13o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch13i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch14o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch14i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch15o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch15i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch16o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch16i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -263,6 +359,18 @@ begin
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
......
......@@ -264,4 +264,159 @@ peripheral {
};
};
reg {
name = "CH11 output";
prefix = "ch11o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH11 input";
prefix = "ch11i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH12 output";
prefix = "ch12o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH12 input";
prefix = "ch12i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH13 output";
prefix = "ch13o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH13 input";
prefix = "ch13i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH14 output";
prefix = "ch14o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH14 input";
prefix = "ch14i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH15 output";
prefix = "ch15o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH15 input";
prefix = "ch15i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH16 output";
prefix = "ch16o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH16 input";
prefix = "ch16i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
......@@ -134,6 +134,7 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../pulse_gen/rtl/pulse_gen.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
......
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
......@@ -7,7 +7,7 @@ modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../old_rep_test"
"../../pulse_gen",
"../../pulse_generator",
"../../rtm_detector",
"../../bicolor_led_ctrl",
......
......@@ -183,31 +183,31 @@ NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##-- Schematics name: FPGA_BLO_IN_*
##---- renamed to fpga_blo_in_i[*]
##-------------------
#NET "fpga_blo_in_i[1]" LOC = Y9;
#NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33";
#NET "fpga_blo_in_i[2]" LOC = AA10;
#NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33";
#NET "fpga_blo_in_i[3]" LOC = W12;
#NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33";
#NET "fpga_blo_in_i[4]" LOC = AA6;
#NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33";
#NET "fpga_blo_in_i[5]" LOC = Y7;
#NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33";
#NET "fpga_blo_in_i[6]" LOC = AA8;
#NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33";
#
#NET "fpga_trig_blo_o[1]" LOC = W9;
#NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33";
#NET "fpga_trig_blo_o[2]" LOC = T10;
#NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33";
#NET "fpga_trig_blo_o[3]" LOC = V7;
#NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33";
#NET "fpga_trig_blo_o[4]" LOC = U9;
#NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33";
#NET "fpga_trig_blo_o[5]" LOC = T8;
#NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
#NET "fpga_trig_blo_o[6]" LOC = R9;
#NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
###======================================
###-- VME CONNECTOR SIGNALS
......
This diff is collapsed.
......@@ -43,7 +43,8 @@ entity pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400
g_freq : natural := 400;
g_delay : natural := 0
);
port
(
......@@ -74,12 +75,39 @@ architecture behav of pulse_gen is
-- Signal declarations
--============================================================================
signal freq_cnt : unsigned(f_log2_size(g_freq)-1 downto 0);
signal delay_cnt : unsigned(f_log2_size(g_delay)-1 downto 0);
signal delay_en : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Delay logic
--============================================================================
gen_nodelay: if (g_delay = 0) generate
delay_en <= '0';
end generate gen_nodelay;
gen_delay: if (g_delay > 0) generate
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
elsif (en_i = '1') and (delay_en = '1') then
delay_cnt <= delay_cnt + 1;
if (delay_cnt = g_delay-1) then
delay_en <= '0';
delay_cnt <= (others => '0');
end if;
end if;
end if;
end process p_delay;
end generate gen_delay;
--============================================================================
-- Pulse generation logic
--============================================================================
......@@ -89,7 +117,7 @@ begin
if (rst_n_i = '0') then
freq_cnt <= (others => '0');
pulse_o <= '0';
elsif (en_i = '1') then
elsif (en_i = '1') and (delay_en = '0') then
freq_cnt <= freq_cnt + 1;
pulse_o <= '0';
if (freq_cnt < g_pwidth) then
......
vlib work
vcom -explicit -93 "../rtl/old_rep_test.vhd"
vcom -explicit -93 "../rtl/pulse_gen.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -voptargs="+acc" -lib work work.testbench
......
......@@ -59,24 +59,27 @@ architecture behav of testbench is
-- Component declarations
--============================================================================
component old_rep_test is
component pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 200000000
g_freq : natural := 200000000;
g_delay : natural := 1
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_o : out std_logic
);
end component old_rep_test;
end component pulse_gen;
--============================================================================
-- Signal declarations
--============================================================================
signal clk, rst, pulse : std_logic := '0';
signal clk, rst_n : std_logic := '0';
signal pulse0, pulse1, pulse2 : std_logic := '0';
--==============================================================================
......@@ -84,17 +87,49 @@ architecture behav of testbench is
--==============================================================================
begin
DUT: old_rep_test
DUT0: pulse_gen
generic map
(
g_pwidth => 1,
g_freq => 13
g_freq => 20,
g_delay => 0
)
port map
(
clk_i => clk,
rst_i => rst,
pulse_o => pulse
rst_n_i => rst_n,
en_i => '1',
pulse_o => pulse0
);
DUT1: pulse_gen
generic map
(
g_pwidth => 1,
g_freq => 20,
g_delay => 3
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
en_i => '1',
pulse_o => pulse1
);
DUT2: pulse_gen
generic map
(
g_pwidth => 1,
g_freq => 20,
g_delay => 8
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
en_i => '1',
pulse_o => pulse2
);
p_clk: process
......@@ -105,9 +140,9 @@ begin
p_rst: process
begin
rst <= '1';
rst_n <= '0';
wait for c_reset_width;
rst <= '0';
rst_n <= '1';
wait;
end process p_rst;
......
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst
add wave -noupdate /testbench/pulse
add wave -noupdate -divider internal
add wave -noupdate /testbench/DUT/pulse_cnt
add wave -noupdate /testbench/DUT/pulse
add wave -noupdate /testbench/DUT/freq_cnt
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/pulse0
add wave -noupdate /testbench/pulse1
add wave -noupdate /testbench/pulse2
add wave -noupdate -divider gen0
add wave -noupdate /testbench/DUT0/freq_cnt
add wave -noupdate /testbench/DUT0/delay_cnt
add wave -noupdate /testbench/DUT0/delay_en
add wave -noupdate -divider gen1
add wave -noupdate /testbench/DUT1/freq_cnt
add wave -noupdate /testbench/DUT1/delay_cnt
add wave -noupdate /testbench/DUT1/delay_en
add wave -noupdate -divider gen2
add wave -noupdate /testbench/DUT2/freq_cnt
add wave -noupdate /testbench/DUT2/delay_cnt
add wave -noupdate /testbench/DUT2/delay_en
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {40 ns} 0}
WaveRestoreCursors {{Cursor 1} {2623 ns} 0}
configure wave -namecolwidth 194
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -23,4 +33,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {18484 ns} {20080 ns}
WaveRestoreZoom {0 ns} {105 us}
......@@ -107,30 +107,34 @@ DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GM1
DItemRevisionGUID=
[GeneratedDocument8]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GTL
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GM7
DItemRevisionGUID=
[GeneratedDocument9]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GTO
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GTL
DItemRevisionGUID=
[GeneratedDocument10]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GTS
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GTO
DItemRevisionGUID=
[GeneratedDocument11]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.LDP
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GTS
DItemRevisionGUID=
[GeneratedDocument12]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.REP
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.LDP
DItemRevisionGUID=
[GeneratedDocument13]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.RUL
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.REP
DItemRevisionGUID=
[GeneratedDocument14]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.RUL
DItemRevisionGUID=
[GeneratedDocument15]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.TXT
DItemRevisionGUID=
......@@ -478,7 +482,7 @@ OutputDocumentPath9=
OutputVariantName9=[No Variations]
OutputDefault9=0
Configuration9_Name1=OutputConfigurationParameter1
Configuration9_Item1=AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=500000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=50|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973834~1,16777217~1,16842751~1,16973835~1,16908289~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=50|Record=GerberView|SoftwareArcs=False|Sorted=False
Configuration9_Item1=AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=500000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Metric|IncludeUnconnectedMidLayerPads=False|LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=39|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NumberOfDecimals=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973834~1,16777217~1,16842751~1,16973835~1,16908289~1,16908295~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=39|Record=GerberView|SoftwareArcs=False|Sorted=False
[OutputGroup6]
Name=Report Outputs
......
......@@ -230,12 +230,12 @@
<tr class="front_matter">
<td class="front_matter_column1">Date</td>
<td class="front_matter_column2">:</td>
<td class="front_matter_column3">26/04/2013</td>
<td class="front_matter_column3">29/04/2013</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time</td>
<td class="front_matter_column2">:</td>
<td class="front_matter_column3">16:12:14</td>
<td class="front_matter_column3">15:20:47</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time</td>
......@@ -262,7 +262,7 @@
</table>
</td>
</table>
<hr><a name="IDASAILC"><h2>Summary</h2></a><table>
<hr><a name="IDASA4LC"><h2>Summary</h2></a><table>
<tr>
<th class="column1">Warnings</th>
<th class="column2">Count</th>
......@@ -277,55 +277,55 @@
<th class="column2">Count</th>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAEBILC">Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=1mm) (InNet('BLO_C_1_N'))</a></td>
<td class="column1"><a href="#IDAEB4LC">Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=1mm) (InNet('BLO_C_1_N'))</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDAKBILC">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column1"><a href="#IDAKB4LC">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAQBILC">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column1"><a href="#IDAQB4LC">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDAWBILC">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
<td class="column1"><a href="#IDAWB4LC">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDA2BILC">Hole Size Constraint (Min=0.025mm) (Max=3mm) (All)</a></td>
<td class="column1"><a href="#IDA2B4LC">Hole Size Constraint (Min=0.025mm) (Max=3mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDACCILC">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
<td class="column1"><a href="#IDACC4LC">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAICILC">Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)</a></td>
<td class="column1"><a href="#IDAIC4LC">Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDAOCILC">Silkscreen Over Component Pads (Clearance=0.1mm) (All),(All)</a></td>
<td class="column1"><a href="#IDAOC4LC">Silkscreen Over Component Pads (Clearance=0.1mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAUCILC">Silk to Silk (Clearance=0.254mm) (All),(All)</a></td>
<td class="column1"><a href="#IDAUC4LC">Silk to Silk (Clearance=0.254mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDA0CILC">Net Antennae (Tolerance=0mm) (All)</a></td>
<td class="column1"><a href="#IDA0C4LC">Net Antennae (Tolerance=0mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAADILC">Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
<td class="column1"><a href="#IDAAD4LC">Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDAGDILC">Clearance Constraint (Gap=0.127mm) (All),(All)</a></td>
<td class="column1"><a href="#IDAGD4LC">Clearance Constraint (Gap=0.17mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAMDILC">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
<td class="column1"><a href="#IDAMD4LC">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr>
......
---------------------------------------------------------------------------
NCDrill File Report For: PTS_P2_Board.PcbDoc 26/04/2013 16:13:42
NCDrill File Report For: PTS_P2_Board.PcbDoc 29/04/2013 15:21:44
---------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
......
------------------------------------------------------------------------------------------
Gerber File Extension Report For: PTS_P2_Board.GBR 26/04/2013 16:12:29
Gerber File Extension Report For: PTS_P2_Board.GBR 29/04/2013 15:21:22
------------------------------------------------------------------------------------------
......@@ -12,4 +12,5 @@ Layer Extension Layer Description
.GTS Top Solder
.GBS Bottom Solder
.GM1 Mechanical 1
.GM7 Mechanical 7
------------------------------------------------------------------------------------------
%FSLAX25Y25*%
%MOIN*%
G70*
%FSLAX42Y42*%
%MOMM*%
G71*
G01*
G75*
G04 Layer_Color=16711935*
%ADD10R,0.08465X0.09055*%
%ADD11R,0.07087X0.04528*%
%ADD12C,0.03937*%
%ADD13C,0.01000*%
%ADD14C,0.11811*%
%ADD15C,0.05906*%
%ADD16C,0.13780*%
%ADD17C,0.03937*%
%ADD18C,0.20079*%
%ADD19C,0.00787*%
%ADD20C,0.00984*%
%ADD21R,0.09265X0.09855*%
%ADD22R,0.07887X0.05328*%
%ADD23C,0.12611*%
%ADD24C,0.06706*%
%ADD25C,0.14579*%
%ADD26C,0.04737*%
%ADD27C,0.20879*%
%ADD10R,2.15X2.30*%
%ADD11R,1.80X1.15*%
%ADD12C,1.00*%
%ADD13C,0.25*%
%ADD14C,3.00*%
%ADD15C,1.50*%
%ADD16C,3.50*%
%ADD17C,1.00*%
%ADD18C,5.10*%
%ADD19C,0.20*%
%ADD20C,0.25*%
%ADD21R,2.35X2.50*%
%ADD22R,2.00X1.35*%
%ADD23C,3.20*%
%ADD24C,1.70*%
%ADD25C,3.70*%
%ADD26C,1.20*%
%ADD27C,5.30*%
D23*
X196850Y157480D02*
X5000Y4000D02*
D03*
X381890D02*
X9700D02*
D03*
X11811D02*
X300D02*
D03*
D24*
X281811Y50906D02*
X7158Y1293D02*
D03*
X291811D02*
X7412D02*
D03*
X301811D02*
X7666D02*
D03*
X311811D02*
X7920D02*
D03*
X321811D02*
X8174D02*
D03*
X331811D02*
X8428D02*
D03*
X341811D02*
X8682D02*
D03*
X351811D02*
X8936D02*
D03*
X201811D02*
X5126D02*
D03*
X211811D02*
X5380D02*
D03*
X221811D02*
X5634D02*
D03*
X231811D02*
X5888D02*
D03*
X241811D02*
X6142D02*
D03*
X251811D02*
X6396D02*
D03*
X261811D02*
X6650D02*
D03*
X271811D02*
X6904D02*
D03*
X121811D02*
X3094D02*
D03*
X131811D02*
X3348D02*
D03*
X141811D02*
X3602D02*
D03*
X151811D02*
X3856D02*
D03*
X161811D02*
X4110D02*
D03*
X171811D02*
X4364D02*
D03*
X181811D02*
X4618D02*
D03*
X191811D02*
X4872D02*
D03*
X111811D02*
X2840D02*
D03*
X101811D02*
X2586D02*
D03*
X91811D02*
X2332D02*
D03*
X81811D02*
X2078D02*
D03*
X71811D02*
X1824D02*
D03*
X61811D02*
X1570D02*
D03*
X51811D02*
X1316D02*
D03*
X41811D02*
X1062D02*
D03*
X281811Y10906D02*
X7158Y277D02*
D03*
X291811D02*
X7412D02*
D03*
X301811D02*
X7666D02*
D03*
X311811D02*
X7920D02*
D03*
X321811D02*
X8174D02*
D03*
X331811D02*
X8428D02*
D03*
X341811D02*
X8682D02*
D03*
X351811D02*
X8936D02*
D03*
X201811D02*
X5126D02*
D03*
X211811D02*
X5380D02*
D03*
X221811D02*
X5634D02*
D03*
X231811D02*
X5888D02*
D03*
X241811D02*
X6142D02*
D03*
X251811D02*
X6396D02*
D03*
X261811D02*
X6650D02*
D03*
X271811D02*
X6904D02*
D03*
X121811D02*
X3094D02*
D03*
X131811D02*
X3348D02*
D03*
X141811D02*
X3602D02*
D03*
X151811D02*
X3856D02*
D03*
X161811D02*
X4110D02*
D03*
X171811D02*
X4364D02*
D03*
X181811D02*
X4618D02*
D03*
X191811D02*
X4872D02*
D03*
X111811D02*
X2840D02*
D03*
X101811D02*
X2586D02*
D03*
X91811D02*
X2332D02*
D03*
X81811D02*
X2078D02*
D03*
X71811D02*
X1824D02*
D03*
X61811D02*
X1570D02*
D03*
X51811D02*
X1316D02*
D03*
X41811D02*
X1062D02*
D03*
Y40906D02*
Y1039D02*
D03*
X51811D02*
X1316D02*
D03*
X61811D02*
X1570D02*
D03*
X71811D02*
X1824D02*
D03*
X81811D02*
X2078D02*
D03*
X91811D02*
X2332D02*
D03*
X101811D02*
X2586D02*
D03*
X111811D02*
X2840D02*
D03*
X191811D02*
X4872D02*
D03*
X181811D02*
X4618D02*
D03*
X171811D02*
X4364D02*
D03*
X161811D02*
X4110D02*
D03*
X151811D02*
X3856D02*
D03*
X141811D02*
X3602D02*
D03*
X131811D02*
X3348D02*
D03*
X121811D02*
X3094D02*
D03*
X271811D02*
X6904D02*
D03*
X261811D02*
X6650D02*
D03*
X251811D02*
X6396D02*
D03*
X241811D02*
X6142D02*
D03*
X231811D02*
X5888D02*
D03*
X221811D02*
X5634D02*
D03*
X211811D02*
X5380D02*
D03*
X201811D02*
X5126D02*
D03*
X351811D02*
X8936D02*
D03*
X341811D02*
X8682D02*
D03*
X331811D02*
X8428D02*
D03*
X321811D02*
X8174D02*
D03*
X311811D02*
X7920D02*
D03*
X301811D02*
X7666D02*
D03*
X291811D02*
X7412D02*
D03*
X281811D02*
X7158D02*
D03*
X41811Y30906D02*
X1062Y785D02*
D03*
X51811D02*
X1316D02*
D03*
X61811D02*
X1570D02*
D03*
X71811D02*
X1824D02*
D03*
X81811D02*
X2078D02*
D03*
X91811D02*
X2332D02*
D03*
X101811D02*
X2586D02*
D03*
X111811D02*
X2840D02*
D03*
X191811D02*
X4872D02*
D03*
X181811D02*
X4618D02*
D03*
X171811D02*
X4364D02*
D03*
X161811D02*
X4110D02*
D03*
X151811D02*
X3856D02*
D03*
X141811D02*
X3602D02*
D03*
X131811D02*
X3348D02*
D03*
X121811D02*
X3094D02*
D03*
X271811D02*
X6904D02*
D03*
X261811D02*
X6650D02*
D03*
X251811D02*
X6396D02*
D03*
X241811D02*
X6142D02*
D03*
X231811D02*
X5888D02*
D03*
X221811D02*
X5634D02*
D03*
X211811D02*
X5380D02*
D03*
X201811D02*
X5126D02*
D03*
X351811D02*
X8936D02*
D03*
X341811D02*
X8682D02*
D03*
X331811D02*
X8428D02*
D03*
X321811D02*
X8174D02*
D03*
X311811D02*
X7920D02*
D03*
X301811D02*
X7666D02*
D03*
X291811D02*
X7412D02*
D03*
X281811D02*
X7158D02*
D03*
Y20906D02*
Y531D02*
D03*
X291811D02*
X7412D02*
D03*
X301811D02*
X7666D02*
D03*
X311811D02*
X7920D02*
D03*
X321811D02*
X8174D02*
D03*
X331811D02*
X8428D02*
D03*
X341811D02*
X8682D02*
D03*
X351811D02*
X8936D02*
D03*
X201811D02*
X5126D02*
D03*
X211811D02*
X5380D02*
D03*
X221811D02*
X5634D02*
D03*
X231811D02*
X5888D02*
D03*
X241811D02*
X6142D02*
D03*
X251811D02*
X6396D02*
D03*
X261811D02*
X6650D02*
D03*
X271811D02*
X6904D02*
D03*
X121811D02*
X3094D02*
D03*
X131811D02*
X3348D02*
D03*
X141811D02*
X3602D02*
D03*
X151811D02*
X3856D02*
D03*
X161811D02*
X4110D02*
D03*
X171811D02*
X4364D02*
D03*
X181811D02*
X4618D02*
D03*
X191811D02*
X4872D02*
D03*
X111811D02*
X2840D02*
D03*
X101811D02*
X2586D02*
D03*
X91811D02*
X2332D02*
D03*
X81811D02*
X2078D02*
D03*
X71811D02*
X1824D02*
D03*
X61811D02*
X1570D02*
D03*
X51811D02*
X1316D02*
D03*
X41811D02*
X1062D02*
D03*
D26*
X257087Y66929D02*
X6530Y1700D02*
D03*
X311417D02*
X7910D02*
D03*
X156693D02*
X3980D02*
D03*
X107087D02*
X2720D02*
D03*
X322835Y114173D02*
X8200Y2900D02*
D03*
X271654D02*
X6900D02*
D03*
X220473D02*
X5600D02*
D03*
X173228D02*
X4400D02*
D03*
X118110D02*
X3000D02*
D03*
X70866Y113779D02*
X1800Y2890D02*
D03*
D27*
X371811Y10906D02*
X9444Y277D02*
D03*
X21811D02*
X554D02*
D03*
M02*
%FSLAX25Y25*%
%MOIN*%
G70*
%FSLAX42Y42*%
%MOMM*%
G71*
G01*
G75*
G04 Layer_Color=16711935*
%ADD10R,0.08465X0.09055*%
%ADD11R,0.07087X0.04528*%
%ADD12C,0.03937*%
%ADD13C,0.01000*%
%ADD14C,0.11811*%
%ADD15C,0.05906*%
%ADD16C,0.13780*%
%ADD17C,0.03937*%
%ADD18C,0.20079*%
%ADD19C,0.00787*%
%ADD20C,0.00984*%
%ADD21R,0.09265X0.09855*%
%ADD22R,0.07887X0.05328*%
%ADD23C,0.12611*%
%ADD24C,0.06706*%
%ADD25C,0.14579*%
%ADD26C,0.04737*%
%ADD27C,0.20879*%
D19*
X363864Y39757D02*
Y42118D01*
X363077Y42906D01*
X361503D01*
X360716Y42118D01*
Y39757D01*
X361718Y32405D02*
X356995D01*
Y30044D01*
X357782Y29257D01*
X358570D01*
X359357D01*
X360144Y30044D01*
Y32405D01*
Y21618D02*
Y20044D01*
X359357Y19257D01*
X356995D01*
Y21618D01*
X357782Y22406D01*
X358570Y21618D01*
Y19257D01*
X360144Y12284D02*
Y9135D01*
X356995Y12284D01*
Y9135D01*
X365439Y50257D02*
X360716D01*
Y52618D01*
X361503Y53405D01*
X363077D01*
X363864Y52618D01*
Y50257D01*
%ADD10R,2.15X2.30*%
%ADD11R,1.80X1.15*%
%ADD12C,1.00*%
%ADD13C,0.25*%
%ADD14C,3.00*%
%ADD15C,1.50*%
%ADD16C,3.50*%
%ADD17C,1.00*%
%ADD18C,5.10*%
%ADD19C,0.20*%
%ADD20C,0.25*%
%ADD21R,2.35X2.50*%
%ADD22R,2.00X1.35*%
%ADD23C,3.20*%
%ADD24C,1.70*%
%ADD25C,3.70*%
%ADD26C,1.20*%
%ADD27C,5.30*%
%ADD28C,0.10*%
D28*
X-0Y0D02*
Y2000D01*
Y4250D01*
X10000D01*
X-0Y0D02*
X10000D01*
Y4250D01*
M02*
%FSLAX42Y42*%
%MOMM*%
G71*
G01*
G75*
G04 Layer_Color=32768*
%ADD10R,2.15X2.30*%
%ADD11R,1.80X1.15*%
%ADD12C,1.00*%
%ADD13C,0.25*%
%ADD14C,3.00*%
%ADD15C,1.50*%
%ADD16C,3.50*%
%ADD17C,1.00*%
%ADD18C,5.10*%
%ADD19C,0.20*%
%ADD20C,0.25*%
%ADD21R,2.35X2.50*%
%ADD22R,2.00X1.35*%
%ADD23C,3.20*%
%ADD24C,1.70*%
%ADD25C,3.70*%
%ADD26C,1.20*%
%ADD27C,5.30*%
%ADD28C,0.10*%
M02*
%FSLAX25Y25*%
%MOIN*%
G70*
%FSLAX42Y42*%
%MOMM*%
G71*
G01*
G75*
G04 Layer_Color=8388736*
%ADD10R,0.08465X0.09055*%
%ADD11R,0.07087X0.04528*%
%ADD12C,0.03937*%
%ADD13C,0.01000*%
%ADD14C,0.11811*%
%ADD15C,0.05906*%
%ADD16C,0.13780*%
%ADD17C,0.03937*%
%ADD18C,0.20079*%
%ADD19C,0.00787*%
%ADD20C,0.00984*%
%ADD21R,0.09265X0.09855*%
%ADD22R,0.07887X0.05328*%
%ADD23C,0.12611*%
%ADD24C,0.06706*%
%ADD25C,0.14579*%
%ADD26C,0.04737*%
%ADD10R,2.15X2.30*%
%ADD11R,1.80X1.15*%
%ADD12C,1.00*%
%ADD13C,0.25*%
%ADD14C,3.00*%
%ADD15C,1.50*%
%ADD16C,3.50*%
%ADD17C,1.00*%
%ADD18C,5.10*%
%ADD19C,0.20*%
%ADD20C,0.25*%
%ADD21R,2.35X2.50*%
%ADD22R,2.00X1.35*%
%ADD23C,3.20*%
%ADD24C,1.70*%
%ADD25C,3.70*%
%ADD26C,1.20*%
D21*
X322835Y78150D02*
X8200Y1985D02*
D03*
Y95079D02*
Y2415D02*
D03*
X271654Y78150D02*
X6900Y1985D02*
D03*
Y95079D02*
Y2415D02*
D03*
X220472Y78150D02*
X5600Y1985D02*
D03*
Y95079D02*
Y2415D02*
D03*
X173228D02*
X4400D02*
D03*
Y78150D02*
Y1985D02*
D03*
X118110Y95079D02*
X3000Y2415D02*
D03*
Y78150D02*
Y1985D02*
D03*
X70866Y95079D02*
X1800Y2415D02*
D03*
Y78150D02*
Y1985D02*
D03*
D22*
X90551Y120276D02*
X2300Y3055D02*
D03*
Y131693D02*
Y3345D02*
D03*
X137795Y120276D02*
X3500Y3055D02*
D03*
Y131693D02*
Y3345D02*
D03*
X192913Y120276D02*
X4900Y3055D02*
D03*
Y131693D02*
Y3345D02*
D03*
X240158D02*
X6100D02*
D03*
Y120276D02*
Y3055D02*
D03*
X291338Y131693D02*
X7400Y3345D02*
D03*
Y120276D02*
Y3055D02*
D03*
X342520Y131693D02*
X8700Y3345D02*
D03*
Y120276D02*
Y3055D02*
D03*
X90551Y96654D02*
X2300Y2455D02*
D03*
Y108071D02*
Y2745D02*
D03*
X137795Y96654D02*
X3500Y2455D02*
D03*
Y108071D02*
Y2745D02*
D03*
X192913Y96654D02*
X4900Y2455D02*
D03*
Y108071D02*
Y2745D02*
D03*
X240158D02*
X6100D02*
D03*
Y96654D02*
Y2455D02*
D03*
X291338Y108071D02*
X7400Y2745D02*
D03*
Y96654D02*
Y2455D02*
D03*
X342520Y108071D02*
X8700Y2745D02*
D03*
Y96654D02*
Y2455D02*
D03*
X90551Y73032D02*
X2300Y1855D02*
D03*
Y84449D02*
Y2145D02*
D03*
X137795Y73032D02*
X3500Y1855D02*
D03*
Y84449D02*
Y2145D02*
D03*
X192913Y73032D02*
X4900Y1855D02*
D03*
Y84449D02*
Y2145D02*
D03*
X240158D02*
X6100D02*
D03*
Y73032D02*
Y1855D02*
D03*
X291338Y84449D02*
X7400Y2145D02*
D03*
Y73032D02*
Y1855D02*
D03*
X342520Y84449D02*
X8700Y2145D02*
D03*
Y73032D02*
Y1855D02*
D03*
D23*
X196850Y157480D02*
X5000Y4000D02*
D03*
X381890D02*
X9700D02*
D03*
X11811D02*
X300D02*
D03*
D24*
X281811Y50906D02*
X7158Y1293D02*
D03*
X291811D02*
X7412D02*
D03*
X301811D02*
X7666D02*
D03*
X311811D02*
X7920D02*
D03*
X321811D02*
X8174D02*
D03*
X331811D02*
X8428D02*
D03*
X341811D02*
X8682D02*
D03*
X351811D02*
X8936D02*
D03*
X201811D02*
X5126D02*
D03*
X211811D02*
X5380D02*
D03*
X221811D02*
X5634D02*
D03*
X231811D02*
X5888D02*
D03*
X241811D02*
X6142D02*
D03*
X251811D02*
X6396D02*
D03*
X261811D02*
X6650D02*
D03*
X271811D02*
X6904D02*
D03*
X121811D02*
X3094D02*
D03*
X131811D02*
X3348D02*
D03*
X141811D02*
X3602D02*
D03*
X151811D02*
X3856D02*
D03*
X161811D02*
X4110D02*
D03*
X171811D02*
X4364D02*
D03*
X181811D02*
X4618D02*
D03*
X191811D02*
X4872D02*
D03*
X111811D02*
X2840D02*
D03*
X101811D02*
X2586D02*
D03*
X91811D02*
X2332D02*
D03*
X81811D02*
X2078D02*
D03*
X71811D02*
X1824D02*
D03*
X61811D02*
X1570D02*
D03*
X51811D02*
X1316D02*
D03*
X41811D02*
X1062D02*
D03*
X281811Y10906D02*
X7158Y277D02*
D03*
X291811D02*
X7412D02*
D03*
X301811D02*
X7666D02*
D03*
X311811D02*
X7920D02*
D03*
X321811D02*
X8174D02*
D03*
X331811D02*
X8428D02*
D03*
X341811D02*
X8682D02*
D03*
X351811D02*
X8936D02*
D03*
X201811D02*
X5126D02*
D03*
X211811D02*
X5380D02*
D03*
X221811D02*
X5634D02*
D03*
X231811D02*
X5888D02*
D03*
X241811D02*
X6142D02*
D03*
X251811D02*
X6396D02*
D03*
X261811D02*
X6650D02*
D03*
X271811D02*
X6904D02*
D03*
X121811D02*
X3094D02*
D03*
X131811D02*
X3348D02*
D03*
X141811D02*
X3602D02*
D03*
X151811D02*
X3856D02*
D03*
X161811D02*
X4110D02*
D03*
X171811D02*
X4364D02*
D03*
X181811D02*
X4618D02*
D03*
X191811D02*
X4872D02*
D03*
X111811D02*
X2840D02*
D03*
X101811D02*
X2586D02*
D03*
X91811D02*
X2332D02*
D03*
X81811D02*
X2078D02*
D03*
X71811D02*
X1824D02*
D03*
X61811D02*
X1570D02*
D03*
X51811D02*
X1316D02*
D03*
X41811D02*
X1062D02*
D03*
Y40906D02*
Y1039D02*
D03*
X51811D02*
X1316D02*
D03*
X61811D02*
X1570D02*
D03*
X71811D02*
X1824D02*
D03*
X81811D02*
X2078D02*
D03*
X91811D02*
X2332D02*
D03*
X101811D02*
X2586D02*
D03*
X111811D02*
X2840D02*
D03*
X191811D02*
X4872D02*
D03*
X181811D02*
X4618D02*
D03*
X171811D02*
X4364D02*
D03*
X161811D02*
X4110D02*
D03*
X151811D02*
X3856D02*
D03*
X141811D02*
X3602D02*
D03*
X131811D02*
X3348D02*
D03*
X121811D02*
X3094D02*
D03*
X271811D02*
X6904D02*
D03*
X261811D02*
X6650D02*
D03*
X251811D02*
X6396D02*
D03*
X241811D02*
X6142D02*
D03*
X231811D02*
X5888D02*
D03*
X221811D02*
X5634D02*
D03*
X211811D02*
X5380D02*
D03*
X201811D02*
X5126D02*
D03*
X351811D02*
X8936D02*
D03*
X341811D02*
X8682D02*
D03*
X331811D02*
X8428D02*
D03*
X321811D02*
X8174D02*
D03*
X311811D02*
X7920D02*
D03*
X301811D02*
X7666D02*
D03*
X291811D02*
X7412D02*
D03*
X281811D02*
X7158D02*
D03*
X41811Y30906D02*
X1062Y785D02*
D03*
X51811D02*
X1316D02*
D03*
X61811D02*
X1570D02*
D03*
X71811D02*
X1824D02*
D03*
X81811D02*
X2078D02*
D03*
X91811D02*
X2332D02*
D03*
X101811D02*
X2586D02*
D03*
X111811D02*
X2840D02*
D03*
X191811D02*
X4872D02*
D03*
X181811D02*
X4618D02*
D03*
X171811D02*
X4364D02*
D03*
X161811D02*
X4110D02*
D03*
X151811D02*
X3856D02*
D03*
X141811D02*
X3602D02*
D03*
X131811D02*
X3348D02*
D03*
X121811D02*
X3094D02*
D03*
X271811D02*
X6904D02*
D03*
X261811D02*
X6650D02*
D03*
X251811D02*
X6396D02*
D03*
X241811D02*
X6142D02*
D03*
X231811D02*
X5888D02*
D03*
X221811D02*
X5634D02*
D03*
X211811D02*
X5380D02*
D03*
X201811D02*
X5126D02*
D03*
X351811D02*
X8936D02*
D03*
X341811D02*
X8682D02*
D03*
X331811D02*
X8428D02*
D03*
X321811D02*
X8174D02*
D03*
X311811D02*
X7920D02*
D03*
X301811D02*
X7666D02*
D03*
X291811D02*
X7412D02*
D03*
X281811D02*
X7158D02*
D03*
Y20906D02*
Y531D02*
D03*
X291811D02*
X7412D02*
D03*
X301811D02*
X7666D02*
D03*
X311811D02*
X7920D02*
D03*
X321811D02*
X8174D02*
D03*
X331811D02*
X8428D02*
D03*
X341811D02*
X8682D02*
D03*
X351811D02*
X8936D02*
D03*
X201811D02*
X5126D02*
D03*
X211811D02*
X5380D02*
D03*
X221811D02*
X5634D02*
D03*
X231811D02*
X5888D02*
D03*
X241811D02*
X6142D02*
D03*
X251811D02*
X6396D02*
D03*
X261811D02*
X6650D02*
D03*
X271811D02*
X6904D02*
D03*
X121811D02*
X3094D02*
D03*
X131811D02*
X3348D02*
D03*
X141811D02*
X3602D02*
D03*
X151811D02*
X3856D02*
D03*
X161811D02*
X4110D02*
D03*
X171811D02*
X4364D02*
D03*
X181811D02*
X4618D02*
D03*
X191811D02*
X4872D02*
D03*
X111811D02*
X2840D02*
D03*
X101811D02*
X2586D02*
D03*
X91811D02*
X2332D02*
D03*
X81811D02*
X2078D02*
D03*
X71811D02*
X1824D02*
D03*
X61811D02*
X1570D02*
D03*
X51811D02*
X1316D02*
D03*
X41811D02*
X1062D02*
D03*
D25*
X371811Y10906D02*
X9444Y277D02*
D03*
X21811D02*
X554D02*
D03*
D26*
X257087Y66929D02*
X6530Y1700D02*
D03*
X311417D02*
X7910D02*
D03*
X156693D02*
X3980D02*
D03*
X107087D02*
X2720D02*
D03*
X322835Y114173D02*
X8200Y2900D02*
D03*
X271654D02*
X6900D02*
D03*
X220473D02*
X5600D02*
D03*
X173228D02*
X4400D02*
D03*
X118110D02*
X3000D02*
D03*
X70866Y113779D02*
X1800Y2890D02*
D03*
M02*
......@@ -98,6 +98,16 @@ Generating : Mechanical 1
Used DCodes :
D19
D28
*************************************************************
*************************************************************
Generating : Mechanical 7
File : PTS_P2_Board.GM7
Adding Layer : Mechanical 7
Used DCodes :
*************************************************************
......@@ -3,4 +3,4 @@ RuleKind=Width|RuleName=Width_GND|Scope=Board|Minimum=10.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width_Normal|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=5.00
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=6.69
......@@ -16,3 +16,4 @@ D24 ROUNDED 67.055 67.055 0.000 FLASH 0.000
D25 ROUNDED 145.795 145.795 0.000 FLASH 0.000
D26 ROUNDED 47.370 47.370 0.000 FLASH 0.000
D27 ROUNDED 208.787 208.787 0.000 FLASH 0.000
D28 ROUNDED 3.937 3.937 0.000 LINE 0.000
Output: NC Drill Files
Type : NC Drill
From : Project [PTS_P2_Board.PrjPCB]
Generated File[PTS_P2_Board.TXT]
Generated File[PTS_P2_Board.DRL]
Generated File[PTS_P2_Board.LDP]
Generated File[PTS_P2_Board.DRR]
Output: Bill of Materials
Type : BOM
From : Variant [[No Variations]] of Project [PTS_P2_Board.PrjPCB]
Files Generated : 4
Files Generated : 0
Documents Printed : 0
Finished Output Generation At 16:13:42 On 26/04/2013
Finished Output Generation At 11:21:07 AM On 5/3/2013
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment