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Commit c76d3cd3 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Started reimplementation of I2C bridge, i2c_slave unit works in simulation and synthesizes.

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hdl/glitch_filt/Manifest.py 0 → 100644
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modules = {"local" : "rtl"}
hdl/glitch_filt/rtl/Manifest.py 0 → 100644
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files = "glitch_filt.vhd"
hdl/glitch_filt/rtl/glitch_filt.vhd 0 → 100644
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--==============================================================================
-- CERN (BE-CO-HT)
-- Glitch filter with selectable length
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end entity glitch_filt;
architecture behav of glitch_filt is
--============================================================================
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
signal degl_dat : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Glitch filtration logic
--============================================================================
-- First, assign the current sample of the glitch filter
glitch_filt(0) <= dat_i;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
p_glitch_filt: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
glitch_filt(g_len downto 1) <= (others => '0');
else
glitch_filt(g_len downto 1) <= glitch_filt(g_len-1 downto 0);
end if;
end if;
end process p_glitch_filt;
end generate gen_glitch_filt;
-- and set the data output based on the state of the glitch filter
p_output: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
dat_o <= '0';
elsif (glitch_filt = (glitch_filt'range => '1')) then
dat_o <= '1';
elsif (glitch_filt = (glitch_filt'range => '0')) then
dat_o <= '0';
end if;
end if;
end process p_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/glitch_filt/sim/run.do 0 → 100644
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vlib work
vcom -explicit -93 "../../old_rep_test/rtl/pulse_gen.vhd"
vcom -explicit -93 "../rtl/glitch_filt.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 100 us
wave zoomfull
hdl/glitch_filt/sim/testbench.vhd 0 → 100644
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--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for glitch filter
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 8 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
-- Component declarations
--============================================================================
component glitch_filt is
generic
(
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
dat_i : in std_logic;
dat_o : out std_logic
);
end component glitch_filt;
component pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen;
--============================================================================
-- Signal declarations
--============================================================================
signal clk, rst_n, pulse, degl_out : std_logic := '0';
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- DUT INSTANTIATION
cmp_dut: glitch_filt
generic map
(
g_glitch_filt_len => 4
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
dat_i => pulse,
dat_o => degl_out
);
-- PULSE GENERATOR FOR TRIGGER
cmp_pulse_gen: pulse_gen
generic map
(
g_pwidth => 6,
g_freq => 2000
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
pulse_o => pulse
);
-- CLOCK GENERATION
p_clk: process
begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
-- RESET GENERATION
p_rst_n: process
begin
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait;
end process p_rst_n;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/degl_out
add wave -noupdate -divider internal
add wave -noupdate -radix binary /testbench/cmp_dut/glitch_filt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {96049638 ps} 0} {{Cursor 3} {14565308 ps} 0}
configure wave -namecolwidth 195
configure wave -valuecolwidth 68
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {95866190 ps} {96233086 ps}
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hdl/vme64x_i2c/doc/i2cSpecs.tex 0 → 100644
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hdl/vme64x_i2c/rtl/Manifest.py 0 → 100644
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files = [
"i2c_slave.vhd",
"vme64x_i2c.vhd"
]
modules = {
"local" : "../../glitch_filt"
}
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hdl/vme64x_i2c/rtl/i2c_bit.vhd 0 → 100644
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the fsm for the recognition of a bit. It offers some
-- interrupting lines to the upper level (i2c_slave_core.vhd)
-- which is responsible for managing byte level transactions
--
-- Dependencies: The inputs should be debounced: i2c_debouncer.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- 0.1 - Module works with no reported issues.
-- 1.0 - Code revamped. Now is clearer and easier to read.
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_bit is
port
(
rst_i : in std_logic;
clk_i : in std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
tx_i : in std_logic;
rx_o : out std_logic;
start_o : out std_logic;
stop_o : out std_logic;
done_o : out std_logic
);
end entity i2c_bit;
architecture behav of i2c_bit is
component i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic;
glitch_mask : in std_logic_VECTOR(g_LENGTH - 1 downto 0)
);
end component i2c_debouncer;
type t_state is (
R0_RESET,
S0_IDLE,
S1A_HIGH_TMP,
S1A_HIGH,
S1B_LOW_TMP,
S1B_LOW,
S2A_START_TMP,
S2A_START,
S2B_STOP_DETECT,
Q1_ERROR
);
-- It specifies the maximum number of stages that will be employed for
-- deglitching. Clocked with clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
-- Three delay stages out of six
constant c_GLITCH_MASK : std_logic_VECTOR (5 downto 0) := "000111";
signal sda_degl : std_logic;
signal sda_degl_d0 : std_logic;
signal scl_degl : std_logic;
signal scl_degl_d0 : std_logic;
signal state : t_state;
signal scl_rising : std_logic;
signal scl_falling : std_logic;
begin
cmp_scl_debouncer: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => clk_i,
input => scl_i,
output => scl_degl,
glitch_mask => c_GLITCH_MASK
);
cmp_sda_debounce: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => clk_i,
input => sda_i,
output => sda_degl,
glitch_mask => c_GLITCH_MASK
);
p_degl_delay: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
sda_degl_d0 <= '0';
scl_degl_d0 <= '0';
else
sda_degl_d0 <= sda_degl;
scl_degl_d0 <= scl_degl;
end if;
end if;
end process p_degl_delay;
p_fsm: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
state <= ST_IDLE;
start_o <= '0';
stop_o <= '0';
rcved_o <= '0';
done_o <= '0';
else
case state is
when ST_IDLE =>
when others =>
end case;
end if;
end if;
end process p_fsm;
-- -- This is the process that samples the scl for detecting
-- -- rise and falling edges
-- reg_proc: process (clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- scl_falling <= '0';
-- scl_rising <= '0';
-- elsif (scl_degl = '0') and (scl_degl_d0 = '1') then
-- scl_falling <= '1';
-- elsif (scl_degl = '1') and (scl_degl_d0 = '0') then
-- scl_rising <= '1';
-- else
-- scl_falling <= '0';
-- scl_rising <= '0';
-- end if;
-- end if;
-- end process;
-- -- Combinatorial process to update the outputs.
-- p_comb_output: process(state)
-- begin
-- start_o <= '0';
-- stop_o <= '0';
-- rcved_o <= '0';
-- done_o <= '0';
--
-- case state is
--
-- when R0_RESET =>
-- null;
--
-- when S0_IDLE =>
-- null;
--
-- when S1A_HIGH =>
-- rcved_o <= '1';
-- done_o <= '1';
--
-- when S1B_LOW =>
-- rcved_o <= '0';
-- done_o <= '1';
--
-- when S2A_START =>
-- start_o <= '1';
-- done_o <= '1';
--
-- when S2B_STOP_DETECT =>
-- stop_o <= '1';
-- done_o <= '1';
--
-- when Q1_ERROR =>
-- null;
--
-- when others =>
-- null;
--
-- end case;
-- end process p_comb_output;
-- -- The fsm of this module, later on the sda sampled line is
-- -- validated in the falling edge of scl.
-- p_fsm: process(clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- state <= R0_RESET;
-- elsif scl_falling = '1' then
-- -- After a detection of a falling edge we update the
-- -- detection of a '0', a '1' and a start condition.
-- case state is
-- when S1A_HIGH_TMP =>
-- state <= S1A_HIGH;
--
-- when S1B_LOW_TMP =>
-- state <= S1B_LOW;
--
-- when S2A_START_TMP =>
-- state <= S2A_START;
--
-- when others =>
-- state <= S0_IDLE;
-- end case;
--
-- elsif (scl_rising = '1') then
-- -- When a rising edge is detected we annotate the first value
-- -- in SDA: either a temporary '0' or '1'
-- if (sda_degl_d0 = '1') then
-- state <= S1A_HIGH_TMP;
-- else
-- state <= S1B_LOW_TMP;
-- end if;
--
-- else
-- -- When we are in high level of a scl cycle, we keep on updating
-- -- the FSM
-- if (scl_degl = '1') then
-- case state is
-- -- Just for random bit swapped coverage.
-- when S0_IDLE =>
-- if (sda_degl = '1') then
-- state <= S1A_HIGH_TMP;
-- else
-- state <= S1B_LOW_TMP;
-- end if;
--
-- when S1A_HIGH_TMP =>
-- if sda_degl = '0' then
-- -- The detection of the start condition will be reported
-- -- in the next SCL rising edge.
-- state <= S2A_START_TMP;
-- end if;
--
-- when S1B_LOW_TMP =>
-- if sda_degl = '1' then
-- -- The detection of the pause condition MUST be
-- -- reported immediately.
-- state <= S2B_STOP_DETECT;
-- end if;
--
-- when S2A_START_TMP =>
-- if (sda_degl = '1') then
-- --! This happens if the deglitching is not enough
-- state <= Q1_ERROR;
-- end if;
--
-- when others =>
-- state <= S0_IDLE;
-- end case;
-- else
-- if (scl_degl_d0 = '0') then
-- state <= S0_IDLE;
-- end if;
-- end if;
-- end if;
-- end if;
-- end process p_fsm;
end behav;
hdl/vme64x_i2c/rtl/i2c_debounce.vhd 0 → 100644
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:11:43 10/25/2011
-- Design Name:
-- Module Name: i2c_debounce - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a I2C debouncer. The main difference is that it is
-- intended to filter out low glitches. That means the oppositive
-- from the previous version --debouncer.vhd.
-- This behaviour makes more sense compared on how I2C definition
-- resolves arbitration --conceptually the same as this module.
--
-- A '1' in the glitch_mask means that the bit should be studied.
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
signal input_d0 : STD_LOGIC;
-- The first of this signal is already stable (ff'ed two times at [0])
signal delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
input_d0 <= '0';
delay <= (others => '0');
else
input_d0 <= input;
delay(0) <= input_d0;
delay(g_length-1 downto 1) <= delay(g_length-2 downto 0);
end if;
end if;
end process;
p_output: process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
output <= '1';
else
-- We can deglitch either zeros or ones
if ( (delay and glitch_mask) = glitch_mask
or (not(delay) and glitch_mask) = glitch_mask) then
output <= delay(0);
else
-- Internall pull-up of the pin
output <= '1';
end if;
end if;
end if;
end process p_output;
end Behavioral;
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--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT CHANGED
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: vme64x_i2c - behav
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vme64x_i2c is
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic;
-- Wishbone master signals
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_we_o : out std_logic;
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(31 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic
);
end vme64x_i2c;
architecture behav of vme64x_i2c is
--============================================================================
-- Component declarations
--============================================================================
-- I2C slave component
-- (use: provide received byte, stores byte to send)
component i2c_slave is
port
(
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- Slave address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_o = '1'
-- '0' - ACK
-- '1' - NACK
ack_n_i : in std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o : out std_logic;
-- Byte to send, should be loaded while done_o = '1'
tx_byte_i : in std_logic_vector(7 downto 0);
-- Received byte, valid after done_o = '1'
rx_byte_o : out std_logic_vector(7 downto 0);
-- Done signal, valid when
-- * received address matches i2c_addr_i, signaling valid op_o;
-- * a byte was received, signaling valid rx_byte_o and an ACK/NACK should be
-- sent to master;
-- * sent a byte, should set tx_byte_i.
done_o : out std_logic
);
end component i2c_slave;
--============================================================================
-- Signal declarations
--============================================================================
-- Slave component signals
signal ack_n : std_logic;
signal op : std_logic;
signal tx_byte : std_logic_vector(7 downto 0);
signal rx_byte : std_logic_vector(7 downto 0);
signal done : std_logic;
begin
--============================================================================
-- Slave component instantiation and connection
--============================================================================
cmp_i2c_slave: i2c_slave
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_en_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_en_o,
-- Slave address
i2c_addr_i => i2c_addr_i,
-- ACK input, should be set after done_o = '1'
-- '0' - ACK
-- '1' - NACK
ack_n_i => ack_n,
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o => op,
-- Byte to send, should be loaded while done_o = '1'
tx_byte_i => tx_byte,
-- Received byte, valid after done_o = '1'
rx_byte_o => rx_byte,
-- Done signal, valid when
-- * received address matches i2c_addr_i, signaling valid op_o;
-- * a byte was received, signaling valid rx_byte_o and an ACK/NACK should be
-- sent to master;
-- * sent a byte, should set tx_byte_i.
done_o => done
);
end behav;
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vlib work
vcom -explicit -93 "../../glitch_filt/rtl/glitch_filt.vhd"
vcom -explicit -93 "../rtl/i2c_slave.vhd"
vcom -explicit -93 "i2c_master_bit_ctrl.vhd"
vcom -explicit -93 "i2c_master_byte_ctrl.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 1 ms
wave zoomfull
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hdl/vme64x_i2c/sim/wave.do 0 → 100644
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/rst
add wave -noupdate /testbench/txb
add wave -noupdate /testbench/rxb
add wave -noupdate /testbench/mst_sta
add wave -noupdate /testbench/mst_sto
add wave -noupdate /testbench/mst_rd
add wave -noupdate /testbench/mst_wr
add wave -noupdate /testbench/mst_ack
add wave -noupdate /testbench/mst_dat_in
add wave -noupdate /testbench/mst_dat_out
add wave -noupdate /testbench/mst_cmd_ack
add wave -noupdate /testbench/ack_fr_slv
add wave -noupdate /testbench/addr
add wave -noupdate /testbench/slv_done
add wave -noupdate /testbench/rcvd
add wave -noupdate /testbench/tmp
add wave -noupdate /testbench/state_mst
add wave -noupdate /testbench/state_slv
add wave -noupdate -divider master
add wave -noupdate /testbench/cmp_master/scl_i
add wave -noupdate /testbench/cmp_master/scl_o
add wave -noupdate /testbench/cmp_master/scl_oen
add wave -noupdate /testbench/cmp_master/sda_i
add wave -noupdate /testbench/cmp_master/sda_o
add wave -noupdate /testbench/cmp_master/sda_oen
add wave -noupdate /testbench/cmp_master/din
add wave -noupdate /testbench/cmp_master/dout
add wave -noupdate /testbench/cmp_master/c_state
add wave -noupdate -divider {bit ctrl}
add wave -noupdate /testbench/cmp_master/bit_ctrl/c_state
add wave -noupdate /testbench/cmp_master/bit_ctrl/cmd_ack
add wave -noupdate /testbench/cmp_master/bit_ctrl/clk_en
add wave -noupdate /testbench/cmp_master/bit_ctrl/al
add wave -noupdate /testbench/cmp_master/bit_ctrl/sda_oen
add wave -noupdate /testbench/cmp_master/bit_ctrl/sda_chk
add wave -noupdate /testbench/cmp_master/bit_ctrl/sSDA
add wave -noupdate -divider slave
add wave -noupdate /testbench/DUT/scl_i
add wave -noupdate /testbench/DUT/scl_o
add wave -noupdate /testbench/DUT/scl_en_o
add wave -noupdate /testbench/DUT/sda_i
add wave -noupdate /testbench/DUT/sda_o
add wave -noupdate /testbench/DUT/sda_en_o
add wave -noupdate /testbench/DUT/op_o
add wave -noupdate /testbench/DUT/done_o
add wave -noupdate /testbench/DUT/state
add wave -noupdate -radix hexadecimal /testbench/DUT/txsr
add wave -noupdate -radix hexadecimal -childformat {{/testbench/DUT/rxsr(7) -radix hexadecimal} {/testbench/DUT/rxsr(6) -radix hexadecimal} {/testbench/DUT/rxsr(5) -radix hexadecimal} {/testbench/DUT/rxsr(4) -radix hexadecimal} {/testbench/DUT/rxsr(3) -radix hexadecimal} {/testbench/DUT/rxsr(2) -radix hexadecimal} {/testbench/DUT/rxsr(1) -radix hexadecimal} {/testbench/DUT/rxsr(0) -radix hexadecimal}} -subitemconfig {/testbench/DUT/rxsr(7) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(6) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(5) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(4) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(3) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(2) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(1) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(0) {-height 16 -radix hexadecimal}} /testbench/DUT/rxsr
add wave -noupdate -radix unsigned -childformat {{/testbench/DUT/bit_cnt(2) -radix unsigned} {/testbench/DUT/bit_cnt(1) -radix unsigned} {/testbench/DUT/bit_cnt(0) -radix unsigned}} -subitemconfig {/testbench/DUT/bit_cnt(2) {-height 16 -radix unsigned} /testbench/DUT/bit_cnt(1) {-height 16 -radix unsigned} /testbench/DUT/bit_cnt(0) {-height 16 -radix unsigned}} /testbench/DUT/bit_cnt
add wave -noupdate /testbench/DUT/i2c_addr_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {310584000 ps} 0}
configure wave -namecolwidth 274
configure wave -valuecolwidth 127
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {1050 us}
hdl/vme64x_i2c/syn/Makefile 0 → 100644
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target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo_v2"
syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../top"
]
}
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hdl/vme64x_i2c/syn/conv_ttl_blo_v2.xise 0 → 100644
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project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
hdl/vme64x_i2c/test/i2c_bit_tb.vhd 0 → 100644
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--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 12:07:51 10/26/2011
-- Design Name: i2c slave to wb_master testbench
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
-- Project Name: CTDAH
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
library work;
USE ieee.std_logic_1164.ALL;
USE work.i2c_slave_pkg.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY i2c_bit_tb IS
END i2c_bit_tb;
ARCHITECTURE behavior OF i2c_bit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component i2c_bit
port(
rst_i : IN std_logic;
wb_clk_i : IN std_logic;
sda_i : IN std_logic;
scl_i : IN std_logic;
done_o : OUT std_logic;
start_o : OUT std_logic;
pause_o : OUT std_logic;
rcved_o : OUT std_logic
);
end component;
--Inputs
signal rst_i : std_logic := '0';
signal wb_clk_i : std_logic := '0';
signal sda_i : std_logic := '0';
signal scl_i : std_logic := '0';
--Outputs
signal start_o : std_logic;
signal pause_o : std_logic;
signal rcved_o : std_logic;
signal done_o : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant wb_clk_i_period : time := 50 ns; -- @ 20 MHz
constant scl_i_period : time := 2500 ns; -- @ 400 KHz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2c_bit
PORT MAP (rst_i => rst_i,
wb_clk_i => wb_clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => start_o,
pause_o => pause_o,
rcved_o => rcved_o,
done_o => done_o);
-- Clock process definitions
wb_clk_i_process :process
begin
wb_clk_i <= '1';
wait for wb_clk_i_period/2;
wb_clk_i <= '0';
wait for wb_clk_i_period/2;
end process;
scl_i_process :process
begin
scl_i <= '1';
wait for scl_i_period/2;
scl_i <= '0';
wait for scl_i_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure init_cond is
begin
sda_i <= '1';
scl_i <= 'Z';
end init_cond;
procedure rst is
begin
wait for wb_clk_i_period*2;
rst_i <= '1';
wait for wb_clk_i_period*2;
rst_i <= '0';
wait for wb_clk_i_period*2;
end rst;
procedure start is
begin
sda_i <= '1';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '0';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end start;
procedure addr_send(addr : STD_LOGIC_VECTOR(6 downto 0)) is
begin
for i in 0 to 6 loop
sda_i <= addr(i);
wait for scl_i_period;
end loop;
end addr_send;
procedure pause is
begin
sda_i <= '0';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '1';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end pause;
begin
init_cond;
rst;
start;
addr_send("0101100");
pause;
wait;
end process;
END;
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1 OK WRITE [ADDRESS|0]
1 OK WRITE WISHBONE HIGH
1 OK WRITE WISHBONE LOW
1 OK WRITE READ DATA 0
1 OK WRITE READ DATA 1
1 OK WRITE READ DATA 2
1 OK WRITE READ DATA 3
2 OK READ [ADDRESS|0]
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
hdl/vme64x_i2c/top/Manifest.py 0 → 100644
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files = [
"conv_ttl_blo_v2.ucf",
"conv_ttl_blo_v2.vhd"
]
modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../rtl",
]
}
hdl/vme64x_i2c/top/conv_ttl_blo_v2.ucf 0 → 100644
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