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Conv TTL Blocking
Commits
c782c3fc
Commit
c782c3fc
authored
Apr 04, 2013
by
Theodor-Adrian Stana
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Added test01 (thermometer) support in HDL, pending testing.
parent
ee3b4c61
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5 changed files
with
121 additions
and
77 deletions
+121
-77
conv_ttl_blo_v2.bit
hdl/pts/syn/conv_ttl_blo_v2.bit
+0
-0
conv_ttl_blo_v2.gise
hdl/pts/syn/conv_ttl_blo_v2.gise
+20
-19
conv_ttl_blo_v2.xise
hdl/pts/syn/conv_ttl_blo_v2.xise
+15
-15
conv_ttl_blo_v2.ucf
hdl/pts/top/conv_ttl_blo_v2.ucf
+2
-2
conv_ttl_blo_v2.vhd
hdl/pts/top/conv_ttl_blo_v2.vhd
+84
-41
No files found.
hdl/pts/syn/conv_ttl_blo_v2.bit
View file @
c782c3fc
No preview for this file type
hdl/pts/syn/conv_ttl_blo_v2.gise
View file @
c782c3fc
...
...
@@ -78,35 +78,35 @@
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hdl/pts/syn/conv_ttl_blo_v2.xise
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c782c3fc
...
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xil_pn:seqID=
"
7
"
/>
</file>
<file
xil_pn:name=
"../../vme64x_i2c/rtl/vme64x_i2c.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
11
"
/>
</file>
<file
xil_pn:name=
"../../glitch_filt/rtl/glitch_filt.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
"
/>
</file>
</files>
...
...
hdl/pts/top/conv_ttl_blo_v2.ucf
View file @
c782c3fc
...
...
@@ -260,8 +260,8 @@ NET "FPGA_GAP" IOSTANDARD = LVTTL;
####-------------------
####-- Thermo for UID
####-------------------
##
NET "THERMOMETER" LOC = B1;
## NET "THERMOMETER" IOSTANDARD = "LVCMOS25"
;
NET "THERMOMETER" LOC = B1;
NET "THERMOMETER" IOSTANDARD = LVCMOS33
;
####-------------------
####-- DACs control
####--
...
...
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @
c782c3fc
...
...
@@ -106,7 +106,10 @@ entity conv_ttl_blo_v2 is
-- RTM identifiers, should match with the expected values
-- TODO: add matching
FPGA_RTMM_N
:
in
std_logic_vector
(
2
downto
0
);
FPGA_RTMP_N
:
in
std_logic_vector
(
2
downto
0
)
FPGA_RTMP_N
:
in
std_logic_vector
(
2
downto
0
);
-- DS18B20U+ thermometer bidirectional port
THERMOMETER
:
inout
std_logic
);
end
conv_ttl_blo_v2
;
...
...
@@ -126,42 +129,41 @@ architecture behav of conv_ttl_blo_v2 is
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_nr_masters
:
NATURAL
:
=
1
;
constant
c_nr_slaves
:
NATURAL
:
=
1
;
constant
c_nr_slaves
:
NATURAL
:
=
2
;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word aligned
-----------------------------------------
-- M25P32 [0200-03FF]
-- MULTIBOOT [0080-00CF]
-- I2C_SLAVE [0040-007F]
-- SR [0000-003F]
-- PTS [0000-0004]
-- ONEWIRE [0008-000C]
-----------------------------------------
-- slave order definitions
constant
c_slv_pts_regs
:
natural
:
=
0
;
constant
c_slv_onewire_mst
:
natural
:
=
1
;
-- base address definitions
constant
c_addr_pts_regs
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_addr_i2c_bridge
:
t_wishbone_address
:
=
X"00000040"
;
constant
c_addr_multiboot
:
t_wishbone_address
:
=
X"00000080"
;
constant
c_addr_m25p32
:
t_wishbone_address
:
=
X"00000200"
;
constant
c_addr_pts_regs
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_addr_onewire_mst
:
t_wishbone_address
:
=
x"00000008"
;
-- address mask definitions
-- 64 words per page: 6 + 1 bits
constant
c_mask_pts_regs
:
t_wishbone_address
:
=
X"FFFFFFF0"
;
constant
c_mask_i2c_bridge
:
t_wishbone_address
:
=
X"FFFFFFC0"
;
constant
c_mask_multiboot
:
t_wishbone_address
:
=
X"FFFFFFC0"
;
constant
c_mask_m25p32
:
t_wishbone_address
:
=
X"FFFFFE00"
;
constant
c_mask_pts_regs
:
t_wishbone_address
:
=
x"FFFFFFF8"
;
constant
c_mask_onewire_mst
:
t_wishbone_address
:
=
x"FFFFFFF8"
;
-- addresses constant for Wishbone crossbar
constant
c_addresses
:
t_wishbone_address_array
(
c_nr_slaves
-
1
downto
0
)
constant
c_addresses
:
t_wishbone_address_array
(
c_nr_slaves
-
1
downto
0
)
:
=
(
(
others
=>
c_addr_pts_regs
)
0
=>
c_addr_pts_regs
,
1
=>
c_addr_onewire_mst
);
-- masks constant for Wishbone crossbar
constant
c_masks
:
t_wishbone_address_array
(
c_nr_slaves
-
1
downto
0
)
constant
c_masks
:
t_wishbone_address_array
(
c_nr_slaves
-
1
downto
0
)
:
=
(
(
others
=>
c_mask_pts_regs
)
0
=>
c_mask_pts_regs
,
1
=>
c_mask_onewire_mst
);
--============================================================================
...
...
@@ -304,23 +306,28 @@ architecture behav of conv_ttl_blo_v2 is
signal
cnt_halfsec
:
unsigned
(
25
downto
0
);
signal
led_seq
:
unsigned
(
4
downto
0
);
-- one-wire master signals
signal
owr_pwren
:
std_logic_vector
(
0
downto
0
);
signal
owr_en
:
std_logic_vector
(
0
downto
0
);
signal
owr_in
:
std_logic_vector
(
0
downto
0
);
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf
:
IBUFGDS
generic
map
(
DIFF_TERM
=>
TRUE
,
IBUF_LOW_PWR
=>
TRUE
)
port
map
(
I
=>
FPGA_CLK_P
,
IB
=>
FPGA_CLK_N
,
O
=>
clk_125
);
generic
map
(
DIFF_TERM
=>
TRUE
,
IBUF_LOW_PWR
=>
TRUE
)
port
map
(
I
=>
FPGA_CLK_P
,
IB
=>
FPGA_CLK_N
,
O
=>
clk_125
);
--============================================================================
-- Internal and external reset generation
...
...
@@ -423,7 +430,7 @@ begin
end
process
p_i2c_up
;
--============================================================================
--
Output enable logic
--
PTS registers
--============================================================================
-- Regs to test I2C operation
cmp_pts_regs
:
pts_regs
...
...
@@ -431,15 +438,15 @@ begin
(
rst_n_i
=>
rst_n
,
clk_sys_i
=>
clk_125
,
wb_adr_i
=>
xbar_master_out
(
0
)
.
adr
(
2
downto
2
),
wb_dat_i
=>
xbar_master_out
(
0
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
0
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
0
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
0
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
0
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
0
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
0
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
0
)
.
stall
,
wb_adr_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
adr
(
2
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_pts_regs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
c_slv_pts_regs
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
c_slv_pts_regs
)
.
stall
,
-- PTS control register
pts_ctrl_crrt_test_o
=>
pts_crrt_test
,
...
...
@@ -451,7 +458,7 @@ begin
--============================================================================
-- Instantiation and connection of a Wishbone crossbar module
--============================================================================
--
xbar_master_in(0).stall <= '0';
--
xbar_master_in(0).stall <= '0';
xbar_master_in
(
0
)
.
int
<=
'0'
;
xbar_master_in
(
0
)
.
err
<=
'0'
;
...
...
@@ -620,6 +627,42 @@ begin
line_oen_o
(
1
)
=>
LED_CTRL1_OEN
);
--============================================================================
-- One-wire master instantiation
--============================================================================
cmp_onewire_master
:
wb_onewire_master
generic
map
(
g_interface_mode
=>
CLASSIC
,
g_address_granularity
=>
WORD
,
g_num_ports
=>
1
,
g_ow_btp_normal
=>
"5.0"
,
g_ow_btp_overdrive
=>
"1.0"
)
port
map
(
clk_sys_i
=>
clk_125
,
rst_n_i
=>
rst_n
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_onewire_mst
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
c_slv_onewire_mst
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
c_slv_onewire_mst
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
c_slv_onewire_mst
)
.
we
,
wb_adr_i
=>
xbar_master_out
(
c_slv_onewire_mst
)
.
adr
(
4
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_onewire_mst
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_onewire_mst
)
.
dat
,
wb_ack_o
=>
xbar_master_in
(
c_slv_onewire_mst
)
.
ack
,
wb_int_o
=>
open
,
wb_stall_o
=>
xbar_master_in
(
c_slv_onewire_mst
)
.
stall
,
owr_pwren_o
=>
owr_pwren
,
owr_en_o
=>
owr_en
,
owr_i
=>
owr_in
);
THERMOMETER
<=
'0'
when
(
owr_en
(
0
)
=
'1'
)
else
'Z'
;
owr_in
(
0
)
<=
THERMOMETER
;
--============================================================================
-- RTM detection logic
--============================================================================
...
...
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