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Commit c9a88680 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Made changes to I2C protocol addressing and added Beagle software files and… 

Made changes to I2C protocol addressing and added Beagle software files and trigger LEDs vhdl for testing I2C communication. Switching branches to chipscope I2C comm.
parent 5d0ebcdc
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hdl/IMAGES/image1/.gitignore
View file @ c9a88680
......@@ -16,6 +16,14 @@ project/*/
!project/image1.tcl
#!project/waveform/
# Ignore PlanAhead outputs
# *.data/*
# *.runs/*
# *.cache/*
# *.wlf
# *.jou
# *.log
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
......
hdl/IMAGES/image1/.gitignore~ 0 → 100644
View file @ c9a88680
#Ignore LaTeX trash
#doc/.*
#doc/.*_*
#doc/*.*
#doc/.*.*.swp
#doc/.*.*.swp
#doc/Figures/*.eps
#!doc/*.tex
#!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
!project/image1.gise
!project/image1.xise
!project/image1.tcl
#!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
rtl/.swo
rtl/.swp
test/.swo
test/.swp
test/.*.*.swo
test/.*.*.swp
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ c9a88680
......@@ -220,19 +220,19 @@ NET "SCL_O" LOC = E20;
NET "SCL_OE" LOC = H18;
NET "SCL_OE" IOSTANDARD = "LVTTL";
NET "SCL_OE" DRIVE = "4";
NET "SCL_OE" PULLDOWN;
# NET "SCL_OE" PULLDOWN;
NET "SDA_I" LOC = G20;
NET "SDA_I" IOSTANDARD = "LVTTL";
NET "SDA_O" LOC = F20;
NET "SDA_O" IOSTANDARD = "LVTTL";
NET "SDA_O" SLEW = "FAST";
NET "SDA_O" DRIVE = "4";
NET "SDA_O" PULLUP;
# NET "SDA_O" PULLUP;
NET "SDA_OE" LOC = J19;
NET "SDA_OE" IOSTANDARD = "LVTTL";
NET "SDA_OE" SLEW = "FAST";
NET "SDA_OE" DRIVE = "4";
NET "SDA_OE" PULLDOWN;
# NET "SDA_OE" PULLDOWN;
##-------------------
##-- Geographical Address
##--
......
hdl/IMAGES/image1/project/image1.gise
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hdl/IMAGES/image1/project/image1.xise
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hdl/IMAGES/image1/rtl/image1_core.vhd
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hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ c9a88680
......@@ -71,10 +71,13 @@ package image1_pkg is
constant c_RST_B_CLKS : NATURAL := c_RST_TIME/c_CLKB_PERIOD;
constant c_NUM_MASTERS : NATURAL := 1;
constant c_NUM_SLAVES : NATURAL := 3;
constant c_NUM_SLAVES : NATURAL := 2;
constant c_MASTER_I2C_SLAVE : NATURAL := 0;
constant c_SLAVE_I2C_SLAVE : NATURAL := 0;
-- !!!!!!!!!!!!!!!!
constant c_slave_trigleds_wb : natural := 1;
-- !!!!!!!!!!!!!!!!
constant c_SLAVE_MULTIBOOT : NATURAL := 1;
constant c_SLAVE_M25P32 : NATURAL := 2;
......@@ -94,20 +97,26 @@ package image1_pkg is
constant c_ADDR_M25P32 : t_wishbone_address := X"00000200";
constant c_ADDR_MULTIBOOT : t_wishbone_address := X"00000080";
constant c_ADDR_I2C_SLAVE : t_wishbone_address := X"00000040";
-- !!
constant c_addr_trigleds_wb : t_wishbone_address := X"00000080";
--! 64 words per page: 6 + 1 bits
constant c_MASK_M25P32 : t_wishbone_address := X"FFFFFE00";
constant c_MASK_MULTIBOOT : t_wishbone_address := X"FFFFFFC0";
constant c_MASK_I2C_SLAVE : t_wishbone_address := X"FFFFFFC0";
constant c_MASK_I2C_SLAVE : t_wishbone_address := X"FFFFFFC0";
-- !!!!!!!
constant c_mask_trigleds_wb : t_wishbone_address := X"FFFFFFC0";
constant c_addresses : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (c_ADDR_M25P32,
c_ADDR_MULTIBOOT,
:= (--c_ADDR_M25P32,
--c_ADDR_MULTIBOOT,
c_addr_trigleds_wb,
c_ADDR_I2C_SLAVE);
constant c_masks : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (c_MASK_M25P32,
c_MASK_MULTIBOOT,
:= (--c_MASK_M25P32,
-- c_MASK_MULTIBOOT,
c_mask_trigleds_wb,
c_MASK_I2C_SLAVE);
component basic_trigger_top
......@@ -127,7 +136,7 @@ package image1_pkg is
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level : in STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
......@@ -189,7 +198,8 @@ package image1_pkg is
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0));
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end component;
component m25p32_top
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
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This diff is collapsed.
hdl/IMAGES/image1/test/log/i2c_master_driver.txt
View file @ c9a88680
......@@ -2,74 +2,10 @@
1 OK READ WISHBONE HIGH
1 OK READ WISHBONE LOW
1 OK READ [ADDRESS|0]
2 OK READ [ADDRESS|0]
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
3 OK WRITE [ADDRESS|0]
3 OK WRITE WISHBONE HIGH
3 OK WRITE WISHBONE LOW
3 OK WRITE READ DATA 0
3 OK WRITE READ DATA 1
3 OK WRITE READ DATA 2
3 OK WRITE READ DATA 3
4 OK READ [ADDRESS|0]
4 OK READ WISHBONE HIGH
4 OK READ WISHBONE LOW
4 OK READ [ADDRESS|0]
5 OK WRITE [ADDRESS|0]
5 OK WRITE WISHBONE HIGH
5 OK WRITE WISHBONE LOW
5 OK WRITE READ DATA 0
5 OK WRITE READ DATA 1
5 OK WRITE READ DATA 2
5 OK WRITE READ DATA 3
6 OK READ [ADDRESS|0]
6 OK READ WISHBONE HIGH
6 OK READ WISHBONE LOW
6 OK READ [ADDRESS|0]
7 OK WRITE [ADDRESS|0]
7 OK WRITE WISHBONE HIGH
7 OK WRITE WISHBONE LOW
7 OK WRITE READ DATA 0
7 OK WRITE READ DATA 1
7 OK WRITE READ DATA 2
7 OK WRITE READ DATA 3
8 OK READ [ADDRESS|0]
8 OK READ WISHBONE HIGH
8 OK READ WISHBONE LOW
8 OK READ [ADDRESS|0]
9 OK WRITE [ADDRESS|0]
9 OK WRITE WISHBONE HIGH
9 OK WRITE WISHBONE LOW
9 OK WRITE READ DATA 0
9 OK WRITE READ DATA 1
9 OK WRITE READ DATA 2
9 OK WRITE READ DATA 3
10 OK READ [ADDRESS|0]
10 OK READ WISHBONE HIGH
10 OK READ WISHBONE LOW
10 OK READ [ADDRESS|0]
11 OK WRITE [ADDRESS|0]
11 OK WRITE WISHBONE HIGH
11 OK WRITE WISHBONE LOW
11 OK WRITE READ DATA 0
11 OK WRITE READ DATA 1
11 OK WRITE READ DATA 2
11 OK WRITE READ DATA 3
12 OK READ [ADDRESS|0]
12 OK READ WISHBONE HIGH
12 OK READ WISHBONE LOW
12 OK READ [ADDRESS|0]
13 OK WRITE [ADDRESS|0]
13 OK WRITE WISHBONE HIGH
13 OK WRITE WISHBONE LOW
13 OK WRITE READ DATA 0
13 OK WRITE READ DATA 1
13 OK WRITE READ DATA 2
13 OK WRITE READ DATA 3
14 OK READ [ADDRESS|0]
14 OK READ WISHBONE HIGH
14 OK READ WISHBONE LOW
14 OK READ [ADDRESS|0]
15 OK WRITE [ADDRESS|0]
2 OK WRITE [ADDRESS|0]
2 OK WRITE WISHBONE HIGH
2 OK WRITE WISHBONE LOW
2 OK WRITE READ DATA 0
2 OK WRITE READ DATA 1
2 OK WRITE READ DATA 2
2 OK WRITE READ DATA 3
hdl/IMAGES/image1/top/image1_top.vhd
View file @ c9a88680
......@@ -131,7 +131,7 @@ architecture Behavioral of image1_top is
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
......@@ -207,7 +207,7 @@ begin
fpga_o_blo_en => FPGA_BLO_OE,
fpga_o_ttl_en => FPGA_TRIG_TTL_OE,
fpga_o_inv_en => FPGA_INV_OE,
level => LEVEL,
level_i => LEVEL,
switch_i => s_switch_i(1),
manual_rst_n_o => MR_N,
rtm_i => s_rtm_i);
......
hdl/basic_trigger/rtl/basic_trigger_core.vhd
View file @ c9a88680
......@@ -41,9 +41,29 @@ end basic_trigger_core;
architecture Behavioral of basic_trigger_core is
-- function pulselen
-- return natural is
-- variable v : natural;
-- begin
-- v := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
-- report "pulse length: " & integer'image(v);
-- return v;
-- end pulselen;
--
-- function ledlen
-- return natural is
-- variable v : natural;
-- begin
-- v := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
-- report "LED length: " & integer'image(v);
-- return v;
-- end ledlen;
constant c_PULSE_LENGTH : NATURAL := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
constant c_LED_LENGTH : NATURAL := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
signal s_pulse : STD_LOGIC;
signal s_deglitched_pulse : STD_LOGIC;
......@@ -53,7 +73,7 @@ architecture Behavioral of basic_trigger_core is
begin
s_pulse <= pulse_i;
s_pulse <= pulse_i;
inst_debo: gc_debouncer
generic map( g_LENGTH => 2)
......
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ c9a88680
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
-- Theodor-Adrian Stana
--
-- Create Date: 09:58:06 10/12/2011
-- Design Name: HDL trigger top
......@@ -28,37 +29,39 @@ use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity basic_trigger_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
port (clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1)
);
end basic_trigger_top;
......@@ -102,74 +105,77 @@ architecture Behavioral of basic_trigger_top is
begin
--! Level 0 means TTL_N Switch UP
--! 1 means TTL Switch DOWN
s_level <= level;
led_pw_o <= '0';
led_err_o <= '1';
led_ttl_o <= not(s_level);
led_link_up_o <= not(s_locked);
led_pps_o <= '1';
led_wr_ok_o <= '1';
--! s_level '1' means TTL input, as we have one inverter in the board we
--! invert here.
s_pulse_i_front <= not(pulse_i_front) when s_level = '1' else pulse_i_front;
s_pulse_i <= s_pulse_i_front or not(pulse_i_rear);
fpga_o_en <= s_fpga_o_en when switch_i = '1' else '0';
fpga_o_ttl_en <= s_fpga_o_ttl_en;
fpga_o_inv_en <= s_fpga_o_inv_en;
fpga_o_blo_en <= s_fpga_o_blo_en;
led_o_front <= not(s_led);--! No need of accurate sync, hence we place
led_o_rear <= not(s_led);--! some combinatorial here.
pulse_o_front <= s_pulse_o when level = '1'
else not(s_pulse_o);
pulse_o_rear <= s_pulse_o;
inv_o <= inv_i;--! As we have one Schmitt inverter in the input,
--! and a buffer in the output, there's no need
--! of invert here.
i_repetitors: for i in 1 to g_NUMBER_OF_CHANNELS generate
begin
trigger: basic_trigger_core
port map (
wb_rst_i => rst_i,
wb_clk_i => clk_i,
pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i),
pulse_n_o => s_pulse_n_o(i),
crop_o => open,
led_o => s_led(i));
end generate i_repetitors;
--! @brief Process to lock the enables so to avoid output glitches
--! on the startup.
--! @param clk_i Main clock used in this clock domain.
p_reset_chain : process(clk_i) is
begin
if rising_edge(clk_i) then
if rst_i = '1' then
--! First we reset the FPGA general output enable
--! Then we let one clock delay for the rest of signals
manual_rst_n_o <= '0';
s_fpga_o_en <= '0';
s_fpga_o_ttl_en <= '0';
s_fpga_o_inv_en <= '0';
s_fpga_o_blo_en <= '0';
else
manual_rst_n_o <= '1';
s_fpga_o_en <= '1';
s_fpga_o_ttl_en <= s_fpga_o_en;
s_fpga_o_inv_en <= s_fpga_o_en;
s_fpga_o_blo_en <= s_fpga_o_en;
end if;
end if;
end process p_reset_chain;
--! level_i 0 means TTL Switch UP
--! 1 means TTL_N Switch DOWN
s_level <= level_i;
led_pw_o <= '0';
led_err_o <= '1';
led_ttl_o <= not(s_level);
led_link_up_o <= not(s_locked);
led_pps_o <= '1';
led_wr_ok_o <= '1';
-- pulse signal assignments
s_pulse_i_front <= pulse_i_front when (s_level = '0') else
not pulse_i_front;
s_pulse_i <= s_pulse_i_front or pulse_i_rear;
fpga_o_en <= s_fpga_o_en when switch_i = '0' else '0';
fpga_o_ttl_en <= s_fpga_o_ttl_en;
fpga_o_inv_en <= s_fpga_o_inv_en;
fpga_o_blo_en <= s_fpga_o_blo_en;
led_o_front <= not(s_led); --! No need of accurate sync, hence we place
led_o_rear <= not(s_led); --! some combinatorial here.
pulse_o_front <= s_pulse_o when s_level = '0' else
not s_pulse_o;
pulse_o_rear <= s_pulse_o;
inv_o <= inv_i;--! As we have one Schmitt inverter in the input,
--! and a buffer in the output, there's no need
--! to invert here.
i_repetitors: for i in 1 to g_NUMBER_OF_CHANNELS generate
begin
trigger: basic_trigger_core
port map
(
wb_rst_i => rst_i,
wb_clk_i => clk_i,
pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i),
pulse_n_o => s_pulse_n_o(i),
crop_o => open,
led_o => s_led(i)
);
end generate i_repetitors;
--! @brief Process to lock the enables so to avoid output glitches
--! on the startup.
--! @param clk_i Main clock used in this clock domain.
p_reset_chain : process(clk_i) is
begin
if rising_edge(clk_i) then
if rst_i = '1' then
--! First we reset the FPGA general output enable
--! Then we let one clock delay for the rest of signals
manual_rst_n_o <= '0';
s_fpga_o_en <= '0';
s_fpga_o_ttl_en <= '0';
s_fpga_o_inv_en <= '0';
s_fpga_o_blo_en <= '0';
else
manual_rst_n_o <= '1';
s_fpga_o_en <= '1';
s_fpga_o_ttl_en <= s_fpga_o_en;
s_fpga_o_inv_en <= s_fpga_o_en;
s_fpga_o_blo_en <= s_fpga_o_en;
end if;
end if;
end process p_reset_chain;
end Behavioral;
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ c9a88680
......@@ -26,8 +26,9 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_slave_top is
generic (g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
port (
generic (g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
port
(
sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
......@@ -63,7 +64,8 @@ entity i2c_slave_top is
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0));
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end i2c_slave_top;
architecture Behavioral of i2c_slave_top is
......
hdl/test_trigleds_wb/test_trigleds.wb 0 → 100644
View file @ c9a88680
peripheral {
name = "Trigger LEDs thru WB interface";
description = "WB for trigger LEDs";
hdl_entity = "test_trigleds_wb";
prefix = "trigleds";
reg {
name = "LED";
prefix = "reg";
field {
name = "Bits";
prefix = "bits";
type = SLV;
size = 6;
};
};
};
hdl/test_trigleds_wb/test_trigleds.wb~ 0 → 100644
View file @ c9a88680
peripheral {
name = "Trigger LEDs thru WB interface";
description = "WB for trigger LEDs";
hdl_entity = "test_triggleds_wb";
prefix = "trigleds";
reg {
name = "LED";
prefix = "reg";
field {
name = "Bits";
prefix = "bits";
type = SLV;
size = 6;
};
};
};
hdl/test_trigleds_wb/test_trigleds_wb.vhd 0 → 100644
View file @ c9a88680
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Trigger LEDs thru WB interface
---------------------------------------------------------------------------------------
-- File : test_trigleds_wb.vhd
-- Author : auto-generated by wbgen2 from test_trigleds.wb
-- Created : Thu Feb 7 13:55:26 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE test_trigleds.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_trigleds_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'Bits' in reg: 'LED'
trigleds_reg_bits_o : out std_logic_vector(5 downto 0)
);
end test_trigleds_wb;
architecture syn of test_trigleds_wb is
signal trigleds_reg_bits_int : std_logic_vector(5 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
trigleds_reg_bits_int <= "000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
if (wb_we_i = '1') then
trigleds_reg_bits_int <= wrdata_reg(5 downto 0);
end if;
rddata_reg(5 downto 0) <= trigleds_reg_bits_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Bits
trigleds_reg_bits_o <= trigleds_reg_bits_int;
rwaddr_reg <= (others => '0');
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
installation/V2/basic_trigger/project/basic_trigger_v2.gise
View file @ c9a88680
......@@ -123,7 +123,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1360141444" xil_pn:in_ck="-3080205394084705193" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-6904032522156638627" xil_pn:start_ts="1360141438">
<transform xil_pn:end_ts="1360170609" xil_pn:in_ck="-3080205394084705193" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-6904032522156638627" xil_pn:start_ts="1360170604">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -132,11 +132,9 @@
<outfile xil_pn:name="basic_trigger_v2_top.ngd"/>
<outfile xil_pn:name="basic_trigger_v2_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1360141471" xil_pn:in_ck="-3080205394084705192" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1360141444">
<transform xil_pn:end_ts="1360170635" xil_pn:in_ck="-3080205394084705192" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1360170609">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="basic_trigger_v2_top.pcf"/>
<outfile xil_pn:name="basic_trigger_v2_top_map.map"/>
......@@ -147,7 +145,7 @@
<outfile xil_pn:name="basic_trigger_v2_top_summary.xml"/>
<outfile xil_pn:name="basic_trigger_v2_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1360141502" xil_pn:in_ck="-659448054332913807" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1360141471">
<transform xil_pn:end_ts="1360170665" xil_pn:in_ck="-659448054332913807" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1360170635">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -161,7 +159,7 @@
<outfile xil_pn:name="basic_trigger_v2_top_pad.txt"/>
<outfile xil_pn:name="basic_trigger_v2_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1360141521" xil_pn:in_ck="529183904242947217" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1360141502">
<transform xil_pn:end_ts="1360170683" xil_pn:in_ck="529183904242947217" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1360170665">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -175,8 +173,10 @@
<transform xil_pn:end_ts="1360141523" xil_pn:in_ck="529183904242934363" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1360141521">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1360141502" xil_pn:in_ck="-3080205394084705324" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1360141495">
<transform xil_pn:end_ts="1360170665" xil_pn:in_ck="-3080205394084705324" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1360170658">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
installation/V2/basic_trigger/project/basic_trigger_v2_top_guide.ncd
View file @ c9a88680
This source diff could not be displayed because it is too large. You can view the blob instead.
installation/V2/basic_trigger/project/basic_trigger_v2_top_summary.html
View file @ c9a88680
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>basic_trigger_v2_top Project Status (02/06/2013 - 10:05:21)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>basic_trigger_v2_top Project Status (02/06/2013 - 18:11:23)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>basic_trigger_v2.xise</TD>
......@@ -440,19 +440,19 @@ System Settings</A>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Feb 6 10:03:57 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/xst.xmsgs?&DataKey=Warning'>616 Warnings (616 new, 0 filtered)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/xst.xmsgs?&DataKey=Info'>22 Infos (22 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Feb 6 10:04:04 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Feb 6 10:04:31 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/map.xmsgs?&DataKey=Info'>6 Infos (6 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Feb 6 10:04:55 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:10:09 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:10:34 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/map.xmsgs?&DataKey=Info'>6 Infos (0 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:10:58 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Feb 6 10:05:02 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Feb 6 10:05:20 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:11:05 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:11:22 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Feb 6 10:05:21 2013</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Feb 6 18:11:23 2013</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/06/2013 - 10:05:21</center>
<br><center><b>Date Generated:</b> 02/06/2013 - 18:11:23</center>
</BODY></HTML>
\ No newline at end of file
installation/V2/basic_trigger/project/iseconfig/basic_trigger_v2.projectmgr
View file @ c9a88680
......@@ -30,13 +30,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a6000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
......@@ -89,13 +89,13 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Configure Target Device</SelectedItem>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a6000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Configure Target Device</CurrentItem>
<CurrentItem></CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000018e0000011d01000000060100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
......
installation/V2/basic_trigger/project/iseconfig/basic_trigger_v2_top.xreport
View file @ c9a88680
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2013-02-06T10:03:39</DateModified>
<DateModified>2013-02-06T18:10:02</DateModified>
<ModuleName>basic_trigger_v2_top</ModuleName>
<SummaryTimeStamp>2013-01-18T14:24:50</SummaryTimeStamp>
<SavedFilePath>/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/basic_trigger_v2_top.xreport</SavedFilePath>
......
installation/V2/basic_trigger/project/par_usage_statistics.html
View file @ c9a88680
......@@ -6,15 +6,15 @@
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>1779</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>141</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>6.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>8.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>8.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>11.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>13.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>13.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>13.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>13.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>13.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>13.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>13.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>13.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>13.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>13.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>13.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>13.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>13.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>13.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>8.7</xtag-par-property-value></TD></TR>
......
sw/beagle-api-linux-i686-v3.09/CHANGES.txt 0 → 100644
View file @ c9a88680
Beagle Protocol Analyzer Software
---------------------------------
Changes for v3.09 (2010/06/25)
------------------------------
- Released separate 32-bit and 64-bit libraries
- Improved threading performance for Python
Changes for v3.08 (2009/08/07)
------------------------------
- .NET 2.0 now required; CLS compliance no longer supported (see README.txt)
- Added support for Python 2.6
Changes for v3.06 (2009/02/16)
------------------------------
- Fixed regression that caused .NET bindings to no longer work
- Fixed rare issue with bg_usb480_digital_out_match function in Python
Changes for v3.05 (2009/01/30)
------------------------------
- Split supported platforms into separate API packages
- Included language examples in API packages instead of in a separate package
Changes for v3.04 (2008/07/18)
------------------------------
- Added support on 64-bit Windows for 32-bit applications
Changes for v3.03 (2008/06/06)
------------------------------
- Added Mac OS X support
- Made improvements to OTG event detection
- Fixed hang in bg_spi_read when SS was inactive but SCK was toggling
- Passing 0 to bg_close will close all open handles
- For Beagle USB 480, resume bus events are now returned with a duration
Changes for v3.02 (2008/01/28)
------------------------------
- Added OTG support for Beagle USB 480
- Improved bg_close to be able to close all open handles with one call
- Minor capture inconsistencies have been fixed
- Support for Python v2.3 has been deprecated (see UPGRADE.txt)
Changes for v3.01 (2007/12/21)
------------------------------
- Made improvements to Rosetta support (see UPGRADE.txt and README.txt)
- Improved host-side-buffer reporting
Changes for v3.00 (2007/10/29)
------------------------------
- Added support for Beagle USB 480 Protocol Analyzer
- Changed API function names, arguments, and constants (see UPGRADE.txt)
- Added firmware revision to BeagleVersion structure
- Added bg_dev_addr to report the device address of the connected analyzer
Changes for v2.00 (2007/04/20)
------------------------------
- Library now requires version 1.1.0.0 of the USB driver (see UPGRADE.txt)
- Added MDIO support
- Changed names of API functions and types (see UPGRADE.txt)
- Library under Linux is now dynamically linked to libusb
- Added support for Python, C#, Visual Basic .NET, Visual Basic 6
- Changed prototypes for all read functions with timing (see UPGRADE.txt)
- Removed BG_READ_ERR_IDLE_TIMEOUT since it was not being used
- Fixed issue where bit timings could be 0 or half the clock period
- Corrected bg_open_ext and bg_version to conform to API documentation
Changes for v1.02 (2006/09/08)
------------------------------
- Fixed memory leak when closing a device (Linux only)
Changes for v1.01 (2006/03/27)
------------------------------
- Fixed issue with beagle_buffers_info where arguments were swapped
Changes for v1.00 (2005/11/01)
------------------------------
- Initial release of the API
sw/beagle-api-linux-i686-v3.09/EXAMPLES.txt 0 → 100644
View file @ c9a88680
Total Phase Beagle Sample Code
------------------------------
Contents
--------
c/ - Examples using C/C++ API
python/ - Python script examples
csharp/ - C# examples
vb.net/ - Visual Basic .NET examples (Windows only)
vb6/ - Visual Basic 6 examples (32-bit Windows only)
Instructions
------------
Each individual examples directory has a README.txt which generally
describes how to run the examples given. Please see those files for
more details.
Every example is relatively short and well-commented. The
application developer is referred to the source code of the examples
for detailed information on how each example operates.
The C, Python, and C# examples include all of the following modules,
while only a subset of these modules are demonstrated in the other
language directories.
API Features
------------
For a detailed explanation of the API features and constructs, please
refer to the Beagle datasheet. For a quick overview on the
differences in API syntax between languages, refer to the README.txt
found in the Beagle Software API package containing the Rosetta Language
Bindings. The Beagle datasheet and Software API package are available on
the Total Phase website.
Short Description
-----------------
* detect
- Detect Beagle devices attached to the system.
* capture_i2c
- Capture I2C data from a Beagle I2C/SPI/MDIO analyzer
* capture_spi
- Capture SPI data from a Beagle I2C/SPI/MDIO analyzer
* capture_mdio
- Capture MDIO data from a Beagle I2C/SPI/MDIO analyzer
* capture_usb12
- Capture USB data from a Beagle USB 12 analyzer
* capture_usb480
- Capture USB data from a Beagle USB 480 analyzer
* capture_usb480_extras
- Capture USB data from a Beagle USB 480 analyzer using
delayed-download mode and hardware filtering
Example
-------
*** capture_i2c ***
Refer to specific language directory README.txt to see how to run
this example under the desired programming language.
> detect
Searching for Beagle adapters...
1 device(s) found:
port=0 (avail) (1095-549045)
> capture_i2c 1024 8
Opened Beagle device on port 0
Sampling rate set to 10000 KHz.
Idle timeout set to 500 ms.
Latency set to 200 ms.
Host interface is high speed.
index,time(ns),I2C,status,<addr:r/w>(*),data0 ... dataN(*)
1,524186100,I2C,( TIMEOUT I2C_NO_STOP )
2,1048474100,I2C,( TIMEOUT I2C_NO_STOP )
3,1336760500,I2C,( I2C_NO_STOP ),[S] <50:w> 00
4,1337556200,I2C,( OK ),[S] <50:r> 00 01 02 03 04 05 06 07 08 09* [P]
5,1862134000,I2C,( TIMEOUT I2C_NO_STOP )
6,2386422000,I2C,( TIMEOUT I2C_NO_STOP )
7,2508685000,I2C,( I2C_NO_STOP ),[S] <50:w> 0a
8,2509465500,I2C,( OK ),[S] <50:r> 0a 0b 0c 0d 0e 0f 10 11 12 13* [P]
sw/beagle-api-linux-i686-v3.09/LICENSE.txt 0 → 100644
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LICENSE AGREEMENT
Beagle Software and Firmware
Copyright (c) 2004-2009 Total Phase, Inc.
All rights reserved.
PREAMBLE:
The accompanying software, firmware, documentation, and related
materials ("Product") are the sole property of Total Phase, Inc.
("Total Phase"). Its use and distribution is subject to the
terms in this License Agreement ("Agreement").
By the use or distribution of the Product, you are consenting to
be bound by the terms of this Agreement. If you do not agree, do
not use or distribute the Product in whole or in part.
TERMS OF USE:
Permission to use, copy, modify, and distribute the Product
is hereby granted, subject to the conditions stated below:
a. The Product is licensed only for use with other Total Phase
products. Any other use is permitted only with the express
written permission of Total Phase.
b. The Product may only be copied unmodified in its entirety,
with all of the files intact including a verbatim copy of this
Agreement. Distribution of modified copies is permitted only
with the express written permission of Total Phase.
c. The Product must not be placed on any publicly-accessible
Internet server including, but not limited to, web servers, ftp
servers, and file sharing systems. Instead, a link should be
placed to the Total Phase website where the latest versions
may be obtained.
d. As a special exemption, a copy of the shared object file
(beagle.dll, beagle.so, cheetah.dll, or cheetah.so) may be
distributed separately from the Product, provided that it is
part of a separate work. Such shared object files carry with
them all of the rights and limitations outlined in this
Agreement, except that it may not be further distributed unless
part of the separate work.
e. Any separate works which include the Product must be plainly
marked as such, and must not be misrepresented as the original
software.
f. You may not modify, translate, reverse-engineer, decompile,
disassemble (except and solely to the extent that an applicable
statute expressly and specifically prohibits such restrictions),
or create derivative works of the Product. A separate work
that only makes use of the unmodified shared object file is not
considered a derivative work.
PROPRIETARY RIGHTS:
The Product is owned by Total Phase and is protected by United
States copyright laws and international treaty provisions. All
copyright, patent, trade secret, trademarks, and other intellectual
and proprietary rights in the Product are and shall remain the
valuable property of Total Phase. You agree to take all necessary
steps to ensure that this property is protected and that the
provisions of this Agreement are not violated by you or by any
person under your control or in your service.
TERMINATION:
Your rights under this license will terminate automatically if you
fail to comply with the terms and conditions set forth herein.
If any provision of this license agreement is held to be
unenforceable, that provision shall be reformed only to the extent
necessary to make it enforceable; and the balance of this license
agreement shall remain in full force and effect.
SAFETY-CRITICAL SYSTEMS POLICY:
The Product is not authorized for use in life support devices or
systems. Life support devices or systems include, but are not
limited to, surgical implants, medical systems, and other
safety-critical systems in which failure of a Total Phase product
could cause personal injury or loss of life.
The Product is not fault-tolerant and is not designed, manufactured
or intended for use or resale in hazardous environments requiring
fail-safe performance, such as in the operation of nuclear facilities,
aircraft navigation or communication systems, air traffic control,
or weapons systems, in which the failure of the Product could lead
directly to death, personal injury, or severe physical or environ-
mental damage. Such use is unauthorized by Total Phase.
Should the Product be used in any such unauthorized manner, Buyer
agrees to indemnify and hold harmless Total Phase, its officers,
employees, affiliates, and distributors from any and all claims
arising from such use, even if such claim alleges that Total Phase
was negligent in the design or manufacture of the Product.
OPEN SOURCE:
The software API portion of the Product makes use of open source
libraries that are not owned by Total Phase and are licensed under
different terms. For specific details, please see the documentation
that is included with the software API package.
DISCLAIMER:
THE PRODUCT IS PROVIDED "AS IS," WITHOUT WARRANTY OF ANY KIND.
THE COPYRIGHT HOLDER(S) AND TOTAL PHASE DISCLAIM ANY AND ALL
WARRANTIES, WHETHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT
LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT HOLDER(S), TOTAL PHASE, ITS
OFFICERS, EMPLOYEES, AFFILIATES, AND DISTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE OF THE PRODUCT, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGE.
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Beagle Protocol Analyzer Software
---------------------------------
Introduction
------------
This software is used to interface with the Beagle Protocol Analyzers
(I2C/SPI/MDIO, USB 12, and USB 480). It provides APIs in a number of
languages for maximum development flexibility.
Directory Structure
-------------------
c/ - C/C++ language binding files and examples
python/ - Python language binding files and examples
csharp/ - C# language binding files and examples
net/ - .NET language binding files
vb.net/ - Visual Basic .NET language binding files and examples
vb6/ - Visual Basic 6 language binding files and examples
The vb.net directory is only available in the 32-bit and 64-bit
Windows packages and the vb6 directory is only available in the
32-bit Windows package.
See the EXAMPLES.txt and the README.txt in each language subdirectory
for details on the included source code that demonstrates the usage of
the API.
USB Driver
----------
Under Windows, ensure the device drivers have been installed before
plugging in any devices or running software. Refer to the Beagle
datasheet for more details on the Windows USB driver.
Under Linux, the libusb library must be installed since the Beagle
software library is dynamically linked to libusb.
Under Mac OS X, a specific kernel driver is not required, but it is
recommended to install the latest OS X updates. The Mac OS X binary
supports Intel versions of Mac OS X 10.4 Tiger or higher.
Features
--------
For explanation and demonstration of the API features and constructs,
please refer to the Beagle datasheet and the example source code available
on the Total Phase website.
C/C++ bindings
--------------
1) Create a new C/C++ project or open an existing project
2) Add beagle.c and beagle.h to the project
3) Place beagle.dll (or beagle.so for Linux/Darwin) in the PATH
4) Place #include "beagle.h" in any module that uses the API
5) Develop, compile, and run your project
Python bindings
---------------
If not already installed, download Python from:
http://www.python.org/2.5/
1) Copy beagle_py.py to a new folder
2) Copy beagle.dll (or beagle.so for Linux/Darwin) to the same folder
3) Create a new script (i.e. program.py)
4) Put the following line in your script file:
from beagle_py import *
5) Develop and run your script
There are two main difference between the Beagle API documented in the
datasheet and the Beagle Python API.
1) The "array" type is used for passing data to and from the Beagle
Python API. See the Python documentation for more information on this
type.
2) Beagle Python API functions can return multiple arguments on
the left hand side. This obviates the need to pass pointers to
output arguments on the right hand side of API functions.
3) There are a variety of ways one can call API functions that have
array arguments.
All arrays can be passed into the API as an ArrayType object or as
a tuple (array, length), where array is an ArrayType object and
length is an integer. The user-specified length would then serve
as the length argument to the API funtion (please refer to the
product datasheet). If only the array is provided, the array's
intrinsic length is used as the argument to the underlying API
function.
The ability to pass in a pre-allocated array along with a separate
length allows the performance-minded programmer to use a single
array for repeated calls to the API, simply changing the contents
of the array and/or the specified length as needed.
Additionally, for arrays that are filled by the API function, an
integer can be passed in place of the array argument and the API
will automatically create an array of that length. All output
arrays, whether passed in or generated, are passed back in the
returned tuple.
The calling conventions for each Beagle Python API function is
documented in the comments of beagle_py.py.
C# bindings
-----------
1) Create a new C/C++ project or open an existing project
2) Add beagle.cs to the project
3) For Windows, place beagle.dll in the PATH;
For Linux rename beagle.so to libbeagle.so and place in the
LD_LIBRARY_PATH
4) Develop, compile, and run your project
Every API function that accepts an array argument must be accompanied
by a separate length field, even though the array itself intrinsically
has a length. See the discussion of the Python API above explaining
the rationale for such an interface.
For C#, structures that contain arrays do not have the length field in
the structure as documented in the datasheet. Instead, the intrinsic
length of the array is used when the structure is an argument to an
API function.
In cases where the API function ignores the structure argument, a dummy
structure should be used instead of null since all versions of the
language do not support null.
.NET and VB.NET bindings
------------------------
Copy beagle.dll and beagle_net.dll to your application development
environment. The beagle.dll contains the APIs themselves and the
beagle_net.dll provides the .NET interface to the APIs. For
detailed documentation of APIs refer to the datasheet and the comments
in the C# (beagle.cs) binding.
Like for C#, every API function that accepts an array argument must
be accompanied by a separate length field. Also as in C#, arrays in
structures use their intrinsic length instead of having a separate
length field in the structure, and dummy structures should be used
instead of passing null when the API is expected to ignore the
structure argument (see above).
Due to the use of unsigned arguments, the .NET bindings are no longer
fully Common Language Specification (CLS) compliant. As a result, for
example, Microsoft .NET 2.0 is required for any VB.NET applications
using the bindings.
Visual Basic 6
--------------
Copy beagle.dll to your application development environment and
integrate the beagle.bas interface layer into your application.
For detailed documentation of the APIs refer to the datasheet
and the comments in the beagle.bas file.
Like for C#, .NET, and VB.NET, every API function that accepts an
array argument must be accompanied by a separate length field. Also
as in C#, .NET and VB.NET, arrays in structures use their intrinsic
length instead of having a separate length field in the structure,
and dummy structures should be used instead of passing null when
the API is expected to ignore the structure argument (see above).
Open Source
-----------
When running on Windows and Mac OS X, this software uses a modified
version of the libusb-0.1.12 open source library. The library is
licensed under LGPL v2.1, the full text of which can be found here:
http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html
To link against a custom version of the library, set the LIBUSBTP
environment variable to the full path of the custom library. The
software will then link against the specified custom library.
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Beagle Protocol Analyzer Software
---------------------------------
Introduction
------------
This document outlines the changes required to upgrade existing
software that is dependent on previous versions of the API. Only
the changes between versions are given in the sections below. New
features are addressed in the datasheet.
Please ensure that all older copies of the Beagle library
(beagle.dll or beagle.so) are removed from your operating system
path before running your upgraded application. This will help
prevent the wrong library from being loaded with your application,
thereby causing a version mismatch.
Upgrade from v1.xx to v2.00
---------------------------
- On Microsoft Windows platforms, ensure that the USB driver
has been upgraded to version 1.1.0.0. See the Beagle datasheet
for details.
- Changes to naming convention of certain types. For example,
BEAGLE_STATUS is now BeagleStatus.
- Constants now have the prefix "BG_" as opposed to "BEAGLE_".
- Function names now have the prefix "bg_" as opposed to "beagle_".
- Changed the function prototype for all read functions with timing
(e.g., bg_spi_read_bit_timing) to include a length argument in
front of every array passed into the function, including
data buffers and timing buffers.
Upgrade from v2.xx to v3.01
---------------------------
- Changed old "bg_usb_" prefix to "bg_usb12_" to better differentiate
the older functions with the newer "bg_usb480_" prefixed functions.
- Added an "events" argument to the bg_usb12_read functions that is
filled with bus events that are seen on the bus. This better segments
status codes from bus events. The various bus event constants have
been renamed from their previous "BG_STATUS_" prefix to "BG_EVENT_".
- Changed Rosetta bindings for C#, .NET, VB.NET, and VB6 such that all
arrays must be also accompanied by a separate length argument. See
the README.txt for details.
- Changed Rosetta bindings for C# to fix type specification for output
arrays (arrays that are filled by the API function). These arrays no
longer need to be passed as "ref array_var_name".
- Changed bg_find_devices_ext function so that each array argument
(devices and unique_ids) is preceded by its own individual length
specification. Please see Beagle datasheet for the behavior
when these lengths are not equal.
- Replaced bg_buffers_avail and bg_buffers_info functions with
bg_host_buffer_size, bg_host_buffer_free, and bg_host_buffer_used.
See the Beagle datasheet for details on these new functions.
- A new event code, BG_USB_TARGET_RESET, has been added and the
bg_usb12_read functions now return it along with the
BG_EVENT_TARGET_DISCONNECT event. Previously there was only
a single BG_READ_USB_TARGET_DISCONNECT constant.
- Changed BG_USB_PID_RESERVE constant to BG_USB_PID_RESERVED.
Upgrade from v3.01 to v3.02
---------------------------
- Support for Python v2.3 has been deprecated. Due to certain
issues with integer types in Python 2.3, large unsigned 32-bit
integers returned from the API will appear as signed negative
integers. Total Phase recommends upgrading to Python 2.4 or
greater since it is possible that support for Python 2.3 may be
entirely dropped in the future.
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sw/beagle-api-linux-i686-v3.09/c/MSVC/capture_usb480.dsp 0 → 100644
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#==========================================================================
# (c) 2005-2008 Total Phase, Inc.
#--------------------------------------------------------------------------
# Project : Beagle Sample Code
# File : Makefile
#--------------------------------------------------------------------------
# Redistribution and use of this file in source and binary forms, with
# or without modification, are permitted.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#==========================================================================
#==========================================================================
# CONFIGURATION
#==========================================================================
OS=$(shell if [ -x /bin/uname ]; then /bin/uname; fi)
ifeq ($(OS),Linux)
SYSLIBS=-ldl
endif
#==========================================================================
# CONSTANTS
#==========================================================================
OUTDIR=_output
CC=gcc -m32
CFLAGS=-Wall -Werror
LD=$(CC)
#==========================================================================
# TARGETS
#==========================================================================
TARGETS=detect capture_i2c capture_spi capture_mdio capture_usb12 \
capture_usb480 capture_usb480_extras
BINARIES=$(TARGETS:%=$(OUTDIR)/%)
all : $(OUTDIR) $(BINARIES)
@if [ -r beagle.so ]; then cp -f beagle.so $(OUTDIR); fi
@if [ -r beagle.dll ]; then cp -f beagle.dll $(OUTDIR); fi
$(BINARIES) : % : $(OUTDIR)/beagle.o %.o
@echo " Linking $@"
@$(LD) -o $@ $^ $(SYSLIBS)
#==========================================================================
# RULES
#==========================================================================
$(OUTDIR)/%.o : %.c
@echo "+++ Compiling $<"
@$(CC) $(CFLAGS) -c -o $@ $<
$(OUTDIR) :
@echo "=== Making output directory."
-@mkdir -p $(OUTDIR)
$(OUT_LIBS) : $(LIBS)
@echo "=== Copying libraries to output directory."
-@cp -f $^ $(OUTDIR)
clean:
@echo "=== Cleaning output directory."
@rm -fr $(OUTDIR)
@rm -f MSVC/*.ncb MSVC/*.opt MSVC/*.plg
@rm -f .bak* *~
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Total Phase Beagle Sample Code
------------------------------
Introduction
------------
This directory contains examples that use the Beagle Rosetta C/C++
language bindings.
Contents
--------
- Makefile for Windows GCC-MinGW32, Linux, and Darwin
- Visual C++ workspace for MSVC++ 6.0 and above
See top level EXAMPLES.txt for descriptions of each example.
Build Instructions
------------------
In each case, PROGRAM can be any of the sample programs, without the
'.c' extension.
Windows Visual C++ 6.0:
1) Open MSVC/Makefile.dsw
2) Build | Batch Build... | Build
3) Optionally place beagle.dll in the PATH
4) _output/PROGRAM
Windows gcc-mingw32:
1) Install GCC MinGW32.
The latest version can be downloaded from the MinGW website:
http://www.mingw.org/
2) Install MSYS
The latest version can be downloaded from the MinGW website:
http://www.mingw.org/
3) Type 'make' at the MSYS command line
4) _output/PROGRAM
Linux and Darwin:
1) Type 'make' at the command line
2) _output/PROGRAM
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#==========================================================================
# (c) 2007-2008 Total Phase, Inc.
#--------------------------------------------------------------------------
# Project : Beagle Sample Code
# File : Makefile
#--------------------------------------------------------------------------
# Redistribution and use of this file in source and binary forms, with
# or without modification, are permitted.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#==========================================================================
#==========================================================================
# CONFIGURATION
#==========================================================================
# Uncomment the following lines for Linux and Darwin
#CSC=mcs
#OPT=-
# Uncomment the following lines for Windows
CSC=csc
OPT=/
#==========================================================================
# CONSTANTS
#==========================================================================
OUTDIR=_output
#==========================================================================
# TARGETS
#==========================================================================
TARGETS=detect capture_i2c \
capture_spi capture_mdio \
capture_usb12 capture_usb480 \
capture_usb480_extras \
BINARIES=$(TARGETS:%=$(OUTDIR)/%)
all : $(OUTDIR) $(BINARIES)
-@if [ -r beagle.so ]; then cp -f beagle.so \
$(OUTDIR)/libbeagle.so; fi
-@if [ -r beagle.dll ]; then cp -f beagle.dll \
$(OUTDIR); fi
$(BINARIES) : % : $(OUTDIR) %.exe
#==========================================================================
# RULES
#==========================================================================
$(OUTDIR)/%.exe : %.cs
$(CSC) $(OPT)out:$@ beagle.cs $<
$(OUTDIR) :
-@mkdir $(OUTDIR)
clean:
rm -fr $(OUTDIR)
rm -f .bak* *~
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sw/beagle-api-linux-i686-v3.09/python/capture_usb12.py 0 → 100644
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sw/beagle-api-linux-i686-v3.09/python/capture_usb480.py 0 → 100644
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sw/beagle-api-linux-i686-v3.09/python/capture_usb480_extras.py 0 → 100644
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sw/beagle-api-linux-i686-v3.09/python/detect.py 0 → 100644
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