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Conv TTL Blocking
Commit ceebd503 authored by gilsoriano's avatar gilsoriano
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Core passes all the write operations. Reads to be checked.

parent 35ae1a29
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Showing with 561 additions and 98 deletions
hdl/m25p32/project/waveform/wave.do
View file @ ceebd503
......@@ -4,64 +4,75 @@ add wave -noupdate -expand -group SPI -radix hexadecimal /m25p32_top_tb/uut/prom
add wave -noupdate -expand -group SPI -radix hexadecimal /m25p32_top_tb/uut/prom_din_i
add wave -noupdate -expand -group SPI -radix hexadecimal /m25p32_top_tb/uut/prom_cs0_b_n_o
add wave -noupdate -expand -group SPI -radix hexadecimal /m25p32_top_tb/uut/prom_cclk_o
add wave -noupdate -divider m25p32_top
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/s_FMI
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/s_SR_m25p32
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_we_i
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_stb_i
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_sel_i
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_cyc_i
add wave -noupdate -group Wishbone -radix hexadecimal -expand -subitemconfig {/m25p32_top_tb/uut/wb_addr_i(6) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(5) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(4) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(3) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(2) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(1) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(0) {-height 17 -radix hexadecimal}} /m25p32_top_tb/uut/wb_addr_i
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_data_i
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_data_o
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_clk
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_rst_i
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_ack_o
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_rty_o
add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_err_o
add wave -noupdate -divider m25p32_core
add wave -noupdate /m25p32_top_tb/wb_clk
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_MEM_fsm
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_MEM_fsm_d0
add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/s_OP
add wave -noupdate -radix hexadecimal -expand -subitemconfig {/m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.CPOL {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.CPHA {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.BREAD {-height 17 -radix unsigned} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.BDATA {-height 17 -radix unsigned} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.BADDR {-height 17 -radix unsigned} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.BINST {-height 17 -radix unsigned}} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_SPI1
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_SPI2
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_SPI3
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_wr_data_i
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/rd_data_o
add wave -noupdate -divider m25p32_regs
add wave -noupdate -radix hexadecimal -expand -subitemconfig {/m25p32_top_tb/uut/inst_m25p32_regs/s_FMI.OPR {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/inst_m25p32_regs/s_FMI.x {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/inst_m25p32_regs/s_FMI.OP {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/inst_m25p32_regs/s_FMI.PG {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/inst_m25p32_regs/s_FMI.SCT {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/inst_m25p32_regs/s_FMI.y {-height 17 -radix hexadecimal}} /m25p32_top_tb/uut/inst_m25p32_regs/s_FMI
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/s_SR_m25p32
add wave -noupdate -divider spi_master_multifield
add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/rst_i
add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/clk_i
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_i
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_inst_reg_o
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/addr_i
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_addr_reg_o
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/data_i
add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_data_reg_o
add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/data_o
add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_STATUS
add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_clk_fsm_d0
add wave -noupdate -expand -subitemconfig {/m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI0_core.BREAD {-height 17 -radix unsigned} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI0_core.BDATA {-height 17 -radix unsigned} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI0_core.BADDR {-height 17 -radix unsigned} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI0_core.BINST {-height 17 -radix unsigned}} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI0_core
add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI1_core
add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI2
add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI3
add wave -noupdate -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/reg_i
add wave -noupdate -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/clk
add wave -noupdate -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/load
add wave -noupdate -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/flush
add wave -noupdate -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/oen_i
add wave -noupdate -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/reg_o
add wave -noupdate -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/reg_int
add wave -noupdate -group {Read counter} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/spi_read_edge_counter/clk_i
add wave -noupdate -group {Read counter} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/spi_read_edge_counter/rst_i
add wave -noupdate -group {Read counter} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/spi_read_edge_counter/en_i
add wave -noupdate -group {Read counter} -radix unsigned /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/spi_read_edge_counter/cnt_o
add wave -noupdate -expand -group m25p32_top -radix hexadecimal /m25p32_top_tb/uut/s_FMI
add wave -noupdate -expand -group m25p32_top -radix hexadecimal /m25p32_top_tb/uut/s_SR_m25p32
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_we_i
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_stb_i
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_sel_i
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_cyc_i
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal -expand -subitemconfig {/m25p32_top_tb/uut/wb_addr_i(6) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(5) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(4) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(3) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(2) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(1) {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/wb_addr_i(0) {-height 17 -radix hexadecimal}} /m25p32_top_tb/uut/wb_addr_i
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_data_i
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_data_o
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_clk
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_rst_i
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_ack_o
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_rty_o
add wave -noupdate -expand -group m25p32_top -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/wb_err_o
add wave -noupdate -group m25p32_core /m25p32_top_tb/wb_clk
add wave -noupdate -group m25p32_core -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_MEM_fsm
add wave -noupdate -group m25p32_core -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_MEM_fsm_d0
add wave -noupdate -group m25p32_core /m25p32_top_tb/uut/inst_m25p32_core/s_OP
add wave -noupdate -group m25p32_core -radix hexadecimal -expand -subitemconfig {/m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.CPOL {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.CPHA {-height 17 -radix hexadecimal} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.BREAD {-height 17 -radix unsigned} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.BDATA {-height 17 -radix unsigned} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.BADDR {-height 17 -radix unsigned} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0.BINST {-height 17 -radix unsigned}} /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0
add wave -noupdate -group m25p32_core -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_SPI1
add wave -noupdate -group m25p32_core -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_SPI2
add wave -noupdate -group m25p32_core -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_SPI3
add wave -noupdate -group m25p32_core -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_wr_data_i
add wave -noupdate -group m25p32_regs -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/s_FMI
add wave -noupdate -group m25p32_regs -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/s_SR_m25p32
add wave -noupdate -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/rst_i
add wave -noupdate -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/clk_i
add wave -noupdate -group spi_master_multifield -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_i
add wave -noupdate -group spi_master_multifield -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_inst_reg_o
add wave -noupdate -group spi_master_multifield -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/addr_i
add wave -noupdate -group spi_master_multifield -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_addr_reg_o
add wave -noupdate -group spi_master_multifield -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/data_i
add wave -noupdate -group spi_master_multifield -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_data_reg_o
add wave -noupdate -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/data_o
add wave -noupdate -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_STATUS
add wave -noupdate -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_clk_fsm_d0
add wave -noupdate -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI0_core
add wave -noupdate -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI1_core
add wave -noupdate -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI2
add wave -noupdate -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI3
add wave -noupdate -group spi_master_multifield -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/reg_i
add wave -noupdate -group spi_master_multifield -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/clk
add wave -noupdate -group spi_master_multifield -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/load
add wave -noupdate -group spi_master_multifield -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/flush
add wave -noupdate -group spi_master_multifield -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/oen_i
add wave -noupdate -group spi_master_multifield -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/reg_o
add wave -noupdate -group spi_master_multifield -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/reg_int
add wave -noupdate -group spi_master_multifield -group {Read counter} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/spi_read_edge_counter/clk_i
add wave -noupdate -group spi_master_multifield -group {Read counter} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/spi_read_edge_counter/rst_i
add wave -noupdate -group spi_master_multifield -group {Read counter} /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/spi_read_edge_counter/en_i
add wave -noupdate -group spi_master_multifield -group {Read counter} -radix unsigned /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/spi_read_edge_counter/cnt_o
add wave -noupdate -expand -group m25p32_top_tb -radix hexadecimal /m25p32_top_tb/s_SPI0
add wave -noupdate -expand -group m25p32_top_tb -radix hexadecimal /m25p32_top_tb/s_SPI1
add wave -noupdate -expand -group m25p32_top_tb -radix hexadecimal /m25p32_top_tb/s_SPI2
add wave -noupdate -expand -group m25p32_top_tb -radix hexadecimal /m25p32_top_tb/s_SPI3
add wave -noupdate -expand -group m25p32_top_tb -radix hexadecimal /m25p32_top_tb/s_page
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser -radix hexadecimal /m25p32_top_tb/tester/SPI0_i
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser -radix hexadecimal -subitemconfig {/m25p32_top_tb/tester/SPI1_i.PUSH_DATA {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.PUSH_ADDR {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.PUSH_INST {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.x {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.READ_MISO {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.SEND_DATA {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.SEND_ADDR {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.SEND_INST {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.SEND_OP {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.y {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.CLK_DIV {-height 17 -radix hexadecimal} /m25p32_top_tb/tester/SPI1_i.z {-height 17 -radix hexadecimal}} /m25p32_top_tb/tester/SPI1_i
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser /m25p32_top_tb/tester/s_SPI0
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser /m25p32_top_tb/tester/s_SPI1
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser -radix hexadecimal /m25p32_top_tb/tester/end_inst_flag_o
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser -radix hexadecimal /m25p32_top_tb/tester/end_addr_flag_o
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser -radix hexadecimal /m25p32_top_tb/tester/end_data_flag_o
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser -radix hexadecimal /m25p32_top_tb/tester/inst_check_o
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser -radix hexadecimal /m25p32_top_tb/tester/addr_check_o
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser -radix hexadecimal /m25p32_top_tb/tester/data_check_o
add wave -noupdate -expand -group m25p32_top_tb -expand -group spi_analyser /m25p32_top_tb/tester/s_spi_count
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {494940633 ps} 0}
WaveRestoreCursors {{Cursor 1} {28727006 ps} 0}
configure wave -namecolwidth 274
configure wave -valuecolwidth 88
configure wave -justifyvalue left
......@@ -76,4 +87,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {945 us}
WaveRestoreZoom {0 ps} {23084406 ps}
hdl/m25p32/rtl/m25p32_core.vhd
View file @ ceebd503
......@@ -41,6 +41,8 @@ use IEEE.NUMERIC_STD.ALL;
use work.m25p32_pkg.ALL;
use work.spi_master_pkg.ALL;
entity m25p32_core is
generic(g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
......@@ -59,6 +61,11 @@ entity m25p32_core is
rd_data_o : out STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
SR_m25p32_i : in STD_LOGIC_VECTOR(r_SR_m25p32'a_length - 1 downto 0);
SPI0_o : out r_SPI0;
SPI1_o : out r_SPI1;
SPI2_o : out r_SPI2;
SPI3_o : out r_SPI3;
OP_o : out STD_LOGIC_VECTOR (r_OP'a_length - 1 downto 0);
FMI_i : in STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0)
);
......@@ -114,6 +121,11 @@ begin
s_SPI2 <= f_SPI2(s_SPI2_slv);
s_SPI3 <= f_SPI3(s_SPI3_slv);
SPI0_o <= s_SPI0;
SPI1_o <= s_SPI1;
SPI2_o <= s_SPI2;
SPI3_o <= s_SPI3;
s_wr_data_i <= f_page(wr_data_i);
inst_spi_master_core: spi_master_core
......@@ -344,7 +356,7 @@ begin
--! operation.
when S2_SPI_INST =>
if s_SPI2.SENT_OP = '1' then
s_MEM_fsm <= Q0_END;
s_MEM_fsm <= S3B_WRDI;
end if;
when S3B_WRDI =>
s_MEM_fsm <= S3_WRDI;
......@@ -365,3 +377,5 @@ begin
end process p_m25p32_fsm;
end Behavioral;
hdl/m25p32/rtl/m25p32_pkg.vhd
View file @ ceebd503
......@@ -79,7 +79,7 @@ package m25p32_pkg is
constant c_BYTES_PER_PAGE_BITS : NATURAL := 8;
constant c_WORDS_PER_PAGE_BITS : NATURAL := c_BYTES_PER_PAGE_BITS - 2;
constant c_PAGE_SIZE : NATURAL := 256; --! Bytes in a page
constant c_PAGE_SIZE : NATURAL := 2**c_BYTES_PER_PAGE_BITS;
--! The four constant below autoadjust to user modifications
constant c_M25P32_ADDR_SIZE : NATURAL := 3;
......@@ -416,7 +416,7 @@ package m25p32_pkg is
BADDR => to_unsigned( 3 , 9),
BINST => to_unsigned( 1 , 9));
constant c_SPI1_PP : r_SPI1 := (PUSH_DATA => '1', PUSH_ADDR => '0',
constant c_SPI1_PP : r_SPI1 := (PUSH_DATA => '1', PUSH_ADDR => '1',
PUSH_INST => '1', x => (others => '0'),
READ_MISO => '0',
SEND_DATA => '1',
......@@ -591,8 +591,8 @@ package body m25p32_pkg is
function f_STD_LOGIC_VECTOR (r_register : r_OP) return STD_LOGIC_VECTOR is
begin
return r_register.OPA
& r_register.OPF;
return r_register.OPF
& r_register.OPA;
end f_STD_LOGIC_VECTOR;
function f_OP(r_register : STD_LOGIC_VECTOR(1 downto 0)) return r_OP is
......
hdl/m25p32/rtl/m25p32_top.vhd
View file @ ceebd503
......@@ -39,6 +39,7 @@ use IEEE.STD_LOGIC_1164.ALL;
use work.m25p32_pkg.ALL;
use work.spi_master_pkg.ALL;
entity m25p32_top is
generic(
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
......@@ -57,6 +58,13 @@ entity m25p32_top is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
SPI0_o : out r_SPI0;
SPI1_o : out r_SPI1;
SPI2_o : out r_SPI2;
SPI3_o : out r_SPI3;
op_finished_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
......@@ -73,6 +81,12 @@ architecture Behavioral of m25p32_top is
signal s_OP : STD_LOGIC_VECTOR (r_OP'a_length - 1 downto 0);
signal s_FMI : STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0);
signal s_SPI0 : r_SPI0;
signal s_SPI1 : r_SPI1;
signal s_SPI2 : r_SPI2;
signal s_SPI3 : r_SPI3;
component m25p32_core is
generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
......@@ -92,6 +106,13 @@ architecture Behavioral of m25p32_top is
rd_data_o : out STD_LOGIC_VECTOR (g_READ_LENGTH*8 - 1 downto 0);
SR_m25p32_i : in STD_LOGIC_VECTOR (r_SR_m25p32'a_length - 1 downto 0);
SPI0_o : out r_SPI0;
SPI1_o : out r_SPI1;
SPI2_o : out r_SPI2;
SPI3_o : out r_SPI3;
OP_o : out STD_LOGIC_VECTOR (r_OP'a_length - 1 downto 0);
FMI_i : in STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0)
);
......@@ -131,6 +152,12 @@ architecture Behavioral of m25p32_top is
begin
op_finished_o <= f_OP(s_OP).OPF;
SPI0_o <= s_SPI0;
SPI1_o <= s_SPI1;
SPI2_o <= s_SPI2;
SPI3_o <= s_SPI3;
inst_m25p32_core: m25p32_core
port map (
......@@ -146,6 +173,10 @@ begin
rd_data_o => s_rd_data,
SR_m25p32_i => s_SR_m25p32,
SPI0_o => s_SPI0,
SPI1_o => s_SPI1,
SPI2_o => s_SPI2,
SPI3_o => s_SPI3,
OP_o => s_OP,
FMI_i => s_FMI
);
......@@ -175,3 +206,5 @@ begin
);
end Behavioral;
hdl/m25p32/test/m25p32_top_tb.vhd
View file @ ceebd503
......@@ -26,16 +26,21 @@ use work.m25p32_pkg.ALL;
use work.spi_master_pkg.ALL;
use work.m25p32_top_tb_pkg.ALL;
use work.spi_analyser_pkg.ALL;
use std.textio.ALL;
entity m25p32_top_tb is
end m25p32_top_tb;
architecture Behavioral of m25p32_top_tb is
file s_file_handler : TEXT;
constant c_log_path : STRING := "../test/log/m25p32_top_tb.log";
-- constant c_log_path : STRING := "/home/carlos/log/m25p32_top_tb.log";
constant sep : CHARACTER := ht;
signal wb_rst_i : STD_LOGIC;
signal s_rst_spi_analyser : STD_LOGIC;
signal wb_clk : STD_LOGIC;
signal wb_rst_i : STD_LOGIC;
signal s_rst_spi_analyser : STD_LOGIC;
signal wb_clk : STD_LOGIC;
signal s_wb_we : STD_LOGIC;
signal s_wb_stb : STD_LOGIC;
......@@ -56,6 +61,7 @@ architecture Behavioral of m25p32_top_tb is
signal s_FMI : r_FMI;
signal s_SR_m25p32 : r_SR_m25p32;
signal s_SR_m25p32_rd : r_SR_m25p32;
--! Signals for the spi_analyser
signal s_SPI0 : r_SPI0;
......@@ -74,6 +80,14 @@ architecture Behavioral of m25p32_top_tb is
signal s_end_data_flag : STD_LOGIC;
signal s_page : r_page;
signal s_SPI3 : r_SPI3;
signal s_op_finished : STD_LOGIC;
signal s_spi_addr : STD_LOGIC_VECTOR(c_M25P32_ADDR_SIZE*8 - 1
downto 0);
signal test_id : NATURAL := 0;
begin
......@@ -95,11 +109,24 @@ begin
wb_rty_o => s_wb_rty,
wb_err_o => s_wb_err,
SPI0_o => s_SPI0,
SPI1_o => s_SPI1,
SPI2_o => s_SPI2,
SPI3_o => s_SPI3,
op_finished_o => s_op_finished,
prom_mosi_o => s_spi_mosi,
prom_cclk_o => s_spi_clk,
prom_cs0_b_n_o => s_spi_cs_n,
prom_din_i => s_spi_miso);
s_rst_spi_analyser <= wb_rst_i
or s_op_finished
or s_SPI1.SEND_OP
or s_SPI2.SENT_OP;
tester : spi_analyser port map(
rst_i => s_rst_spi_analyser,
SPI0_i => s_SPI0,
......@@ -158,23 +185,6 @@ begin
v_reg_data, c_SR_m25p32_addr);
end procedure;
procedure send_operation (
operation : t_operations;
sector: NATURAL;
page : NATURAL) is
variable v_FMI : r_FMI;
begin
v_FMI.OPR := '1';
v_FMI.x := (others => '0');
v_FMI.OP := operation;
v_FMI.PG := to_unsigned(page, c_PAGES_PER_SECTOR_BITS);
v_FMI.SCT := to_unsigned(sector, c_SECTOR_BITS);
v_FMI.y := (others => '0');
wishbone_write(wb_clk, s_wb_we,
s_wb_stb, s_wb_cyc, s_wb_sel,
s_wb_data_i, s_wb_addr,
X"00" & f_STD_LOGIC_VECTOR(v_FMI), c_FMI_addr);
end procedure;
procedure wishbone_write_word_in_page(word : r_word;
pos : NATURAL) is
......@@ -198,8 +208,393 @@ begin
c_DATA_READ_addr);
end procedure;
procedure send_operation (
operation : t_operations;
sector: NATURAL;
page : NATURAL) is
variable v_FMI : r_FMI;
begin
v_FMI.OPR := '1';
v_FMI.x := (others => '0');
v_FMI.OP := operation;
v_FMI.PG := to_unsigned(page, c_PAGES_PER_SECTOR_BITS);
v_FMI.SCT := to_unsigned(sector, c_SECTOR_BITS);
v_FMI.y := (others => '0');
s_spi_addr <= c_ADDR_HEADER_PAD
& STD_LOGIC_VECTOR(v_FMI.SCT)
& STD_LOGIC_VECTOR(v_FMI.PG)
& c_ADDR_FOOTER_PAD;
wishbone_write(wb_clk, s_wb_we,
s_wb_stb, s_wb_cyc, s_wb_sel,
s_wb_data_i, s_wb_addr,
X"00" & f_STD_LOGIC_VECTOR(v_FMI), c_FMI_addr);
end procedure;
procedure check_inst(signal test_id : NATURAL;
operation : t_operations) is
variable v_line_buffer : LINE;
variable v_field : STRING ( 4 downto 1) := (others => ' ');
variable v_operation : STRING ( 4 downto 1) := (others => ' ');
variable v_fail : BOOLEAN := false;
variable v_check : STRING ( 4 downto 1) := "Fail";
variable v_msg : STRING (64 downto 1) := (others => ' ');
begin
v_field := "INST";
if s_inst_check = c_WREN_inst then
v_check := " -- ";
v_field := "WREN";
v_msg(26 downto 1) := "Start of TX: WREN received";
write(v_line_buffer,string'(integer'image(test_id)&sep&v_check&sep
& v_operation&sep&v_field&sep&v_msg));
elsif s_inst_check = c_WRDI_inst then
v_check := " -- ";
v_field := "WRDI";
v_msg(24 downto 1) := "End of TX: WRDI received";
write(v_line_buffer,string'(integer'image(test_id)&sep&v_check&sep
& v_operation&sep&v_field&sep&v_msg));
else
case operation is
when x =>
null;
when RDID =>
v_operation(4 downto 1) := "RDID";
if s_inst_check /= c_RDID_inst then
v_fail := true;
v_msg(42 downto 1) := "Bad instruction code for RDID instruction.";
else
v_check := " OK";
v_msg(47 downto 1) := "RDID instruction received matches with expected";
end if;
when RDSR =>
v_operation(4 downto 1) := "RDSR";
if s_inst_check /= c_RDSR_inst then
v_fail := true;
v_msg(42 downto 1) := "Bad instruction code for RDSR instruction.";
else
v_check := " OK";
v_msg(47 downto 1) := "RDSR instruction received matches with expected";
end if;
when WRSR =>
v_operation(4 downto 1) := "WRSR";
if s_inst_check /= c_WRSR_inst then
v_msg(42 downto 1) := "Bad instruction code for WRSR instruction.";
else
v_check := " OK";
v_msg(47 downto 1) := "WRSR instruction received matches with expected";
end if;
when READ =>
v_operation(4 downto 1) := "READ";
if s_inst_check /= c_READ_inst then
v_msg(42 downto 1) := "Bad instruction code for READ instruction.";
else
v_check := " OK";
v_msg(47 downto 1) := "READ instruction received matches with expected";
end if;
when PP =>
v_operation(2 downto 1) := "PP";
if s_inst_check /= c_PP_inst then
v_msg(40 downto 1) := "Bad instruction code for PP instruction.";
else
v_check := " OK";
v_msg(45 downto 1) := "PP instruction received matches with expected";
end if;
when SE =>
v_operation(2 downto 1) := "SE";
if s_inst_check /= c_SE_inst then
v_msg(40 downto 1) := "Bad instruction code for SE instruction.";
else
v_check := " OK";
v_msg(45 downto 1) := "SE instruction received matches with expected";
end if;
when BE =>
v_operation(2 downto 1) := "BE";
if s_inst_check /= c_BE_inst then
v_msg(40 downto 1) := "Bad instruction code for BE instruction.";
else
v_check := " OK";
v_msg(45 downto 1) := "BE instruction received matches with expected";
end if;
when others =>
null;
end case;
write(v_line_buffer,string'(integer'image(test_id)&sep&v_check&sep
& v_operation&sep&v_field&sep&v_msg));
end if;
if v_fail = true then
assert false report string'("Test"&sep&integer'image(test_id)&sep&v_msg)
severity error;
end if;
writeline(s_file_handler, v_line_buffer);
end procedure;
procedure check_addr(signal test_id : NATURAL;
operation : t_operations) is
variable v_line_buffer : LINE;
variable v_field : STRING ( 4 downto 1) := (others => ' ');
variable v_operation : STRING ( 4 downto 1) := (others => ' ');
variable v_fail : BOOLEAN := false;
variable v_check : STRING ( 4 downto 1) := "Fail";
variable v_msg : STRING (64 downto 1) := (others => ' ');
begin
v_field(4 downto 1) := "ADDR";
case operation is
when READ =>
v_operation(4 downto 1) := "READ";
if s_spi_addr /= s_addr_check then
v_fail := true;
v_msg(43 downto 1) := "Address value mismatch in READ instruction.";
else
v_fail := false;
end if;
when PP =>
v_operation(2 downto 1) := "PP";
if s_spi_addr /= s_addr_check then
v_fail := true;
v_msg(41 downto 1) := "Address value mismatch in PP instruction.";
else
v_fail := false;
end if;
when SE =>
v_operation(2 downto 1) := "SE";
if s_spi_addr /= s_addr_check then
v_fail := true;
v_msg(41 downto 1) := "Address value mismatch in SE instruction.";
else
v_fail := false;
end if;
when others =>
null;
end case;
if v_fail = false then
v_check := " OK";
v_msg(38 downto 1) := "Address received matches with expected";
else
assert false report string'("Test"&sep&integer'image(test_id)&sep&v_msg)
severity error;
end if;
write(v_line_buffer,string'( integer'image(test_id) & sep
& v_check & sep
& v_operation & sep
& v_field & sep
& v_msg));
writeline(s_file_handler, v_line_buffer);
end procedure;
procedure check_data(signal test_id : NATURAL;
operation : t_operations) is
variable v_line_buffer : LINE;
variable v_field : STRING ( 4 downto 1) := (others => ' ');
variable v_operation : STRING ( 4 downto 1) := (others => ' ');
variable v_fail : BOOLEAN := false;
variable v_check : STRING ( 4 downto 1) := "Fail";
variable v_msg : STRING (64 downto 1) := (others => ' ');
variable v_page : r_page;
variable v_ocurreance : BOOLEAN;
begin
v_field(4 downto 1) := "DATA";
case operation is
when WRSR =>
v_page := f_page(s_data_check);
v_operation(4 downto 1) := "WRSR";
if f_STD_LOGIC_VECTOR(s_SR_m25p32) /=
s_data_check (7 downto 0) then
v_msg(46 downto 1) := "SR register value mismatch in WRSR instruction";
else
v_fail := false;
v_check := " OK";
v_msg(42 downto 1) := "SR register received matches with expected";
end if;
write(v_line_buffer,string'( integer'image(test_id) & sep
& v_check & sep
& v_operation & sep
& v_field & sep
& v_msg));
writeline(s_file_handler, v_line_buffer);
when PP =>
v_page := f_page(s_data_check);
v_operation(2 downto 1) := "PP";
for i in 0 to c_PAGE_SIZE/4 - 1 loop
v_msg := (others => ' ');
if v_page /= s_page then
v_fail := true;
v_ocurreance := true;
v_msg(31 downto 1) := string'("Data value mismatch in PP instruction at word " & integer'image(i));
if v_fail = false then
v_check := " OK";
else
assert false report string'("Test"&sep&integer'image(test_id)&sep&v_msg)
severity error;
end if;
write(v_line_buffer,string'( integer'image(test_id) & sep
& v_check & sep
& v_operation & sep
& v_field & sep
& v_msg));
writeline(s_file_handler, v_line_buffer);
end if;
if v_ocurreance = false then
v_fail := false;
end if;
end loop;
when others =>
null;
end case;
end procedure;
procedure check_read(signal test_id : NATURAL;
operation : t_operations) is
variable v_line_buffer : LINE;
variable v_field : STRING ( 4 downto 1) := (others => ' ');
variable v_operation : STRING ( 4 downto 1) := (others => ' ');
variable v_fail : BOOLEAN := false;
variable v_check : STRING ( 4 downto 1) := "Fail";
variable v_msg : STRING (64 downto 1) := (others => ' ');
variable v_ocurreance : BOOLEAN := false;
variable v_page : r_page;
begin
v_field(4 downto 1) := "READ";
case operation is
when RDSR =>
v_page := f_page(s_data_check);
v_operation(4 downto 1) := "RDSR";
if s_SR_m25p32_rd /= s_SR_m25p32 then
v_fail := true;
v_msg(31 downto 1) := "Mismatched SR_m25p32 read value";
assert false report
string'("Test"&sep&integer'image(test_id)&sep&v_msg)
severity error;
else
v_fail := false;
end if;
if v_fail = false then
v_check := " OK";
end if;
write(v_line_buffer,string'(
integer'image(test_id) & sep
& v_check & sep
& v_operation & sep
& v_field & sep
& v_msg));
writeline(s_file_handler, v_line_buffer);
when READ =>
v_page := f_page(s_data_check);
v_operation(4 downto 1) := "READ";
for i in 0 to c_PAGE_SIZE/4 - 1 loop
v_msg := (others => ' ');
if v_page(i) /= s_page(i) then
v_ocurreance := true;
v_fail := true;
v_msg := string'("Mismatched data read at word "
&integer'image(i));
if v_fail = false then
v_check(2 downto 1) := "OK";
end if;
write(v_line_buffer,string'(
integer'image(test_id) & sep
& v_check & sep
& v_operation & sep
& v_field & sep
& v_msg));
writeline(s_file_handler, v_line_buffer);
assert false report string'("Test"&sep&integer'image(test_id)&sep&v_msg)
severity error;
end if;
end loop;
if v_ocurreance = false then
v_fail := false;
if v_fail = false then
v_check := " OK";
end if;
write(v_line_buffer,string'(
integer'image(test_id) & sep
& v_check & sep
& v_operation & sep
& v_field & sep
& v_msg));
writeline(s_file_handler, v_line_buffer);
end if;
when others =>
null;
end case;
end procedure;
procedure write_file_header is
variable v_line_buffer : LINE;
variable v_field : STRING ( 6 downto 1);
variable v_check : STRING ( 7 downto 1);
variable v_operation : STRING ( 4 downto 1);
variable v_msg : STRING ( 9 downto 1);
begin
v_field := "[Stat]";
v_check := "[Check]";
v_operation := "[OP]";
v_msg := "[Message]";
write(v_line_buffer,string'( "[Test]" & sep
& v_check & sep
& v_operation & sep
& v_field & sep
& sep & sep & sep
& sep & sep & sep
& sep & v_msg));
writeline(s_file_handler, v_line_buffer);
end procedure;
procedure check_received_SPI( operation : t_operations;
sector : NATURAL;
page : NATURAL;
signal test_id : NATURAL) is
begin
-- We check WREN
wait until rising_edge(s_end_inst_flag);
check_inst(test_id, operation);
-- We check operation
wait until rising_edge(s_end_inst_flag);
check_inst(test_id, operation);
if (operation = READ)
or (operation = PP)
or (operation = SE) then
wait until rising_edge(s_end_addr_flag);
check_addr(test_id, operation);
end if;
if (operation = WRSR)
or (operation = PP) then
wait until rising_edge(s_end_data_flag);
check_data(test_id, operation);
end if;
-- We check WRDI
wait until rising_edge(s_end_inst_flag);
check_inst(test_id, operation);
end procedure;
procedure wait_until_completion(signal trigger : in STD_LOGIC) is
begin
wait until rising_edge (trigger);
wait for 1*work.m25p32_top_tb_pkg.c_WISHBONE_PERIOD;
wait until rising_edge(wb_clk);
end procedure;
procedure check_and_wait( operation : t_operations;
sector : NATURAL;
page : NATURAL;
signal trigger : STD_LOGIC) is
begin
send_operation(operation, sector, page);
check_received_SPI(operation, sector, page, test_id);
test_id <= test_id + 1;
wait_until_completion(trigger);
end procedure;
begin
file_open(s_file_handler, c_log_path, WRITE_MODE);
--! This line is cosmetic because this register is not loaded in the
--! core until a call to send_instruction procedure is issued.
s_FMI <= c_FMI_default;
......@@ -222,7 +617,7 @@ begin
-------------------------------------------------------------------------------
s_SR_m25p32 <= (WIP => '0',
WEL => '0',
WEL => '0',
BP0 => '1',
BP1 => '1',
BP2 => '1',
......@@ -231,12 +626,11 @@ begin
wait until rising_edge(wb_clk);
write_file_header;
--! Some quick tests
--! [0] Testing WRSR
wishbone_write_SR(s_SR_m25p32);
send_operation(WRSR, 0, 0);
--! Know it should accept the instruction
wait for 512*work.m25p32_top_tb_pkg.c_WISHBONE_PERIOD;
check_and_wait(WRSR, 0, 0, s_op_finished);
--! [1] Testing PP
s_page <= fill_page;
......@@ -246,19 +640,13 @@ begin
wishbone_write_word_in_page(s_page(i), i);
end loop;
wait until rising_edge(wb_clk);
send_operation(PP, 0, 0);
wait for 51200*work.m25p32_top_tb_pkg.c_WISHBONE_PERIOD;
wait until rising_edge(wb_clk);
check_and_wait(PP, 0, 0, s_op_finished);
--! [2] Testing SE
send_operation(SE, 7, 0);
wait for 512*work.m25p32_top_tb_pkg.c_WISHBONE_PERIOD;
wait until rising_edge(wb_clk);
check_and_wait(SE, 7, 0, s_op_finished);
--! [3] Testing BE
send_operation(BE, 0, 0);
wait for 256*work.m25p32_top_tb_pkg.c_WISHBONE_PERIOD;
wait until rising_edge(wb_clk);
check_and_wait(BE, 0, 0, s_op_finished);
assert false report "No error. Simulation ends." severity failure;
end process p_simulation;
......
hdl/m25p32/test/m25p32_top_tb_pkg.vhd
View file @ ceebd503
......@@ -56,6 +56,15 @@ package m25p32_top_tb_pkg is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
--! These lines are offer in top after vpp (VHDL preprocessor) is
--! run with SIMULATION label on.
SPI0_o : out r_SPI0;
SPI1_o : out r_SPI1;
SPI2_o : out r_SPI2;
SPI3_o : out r_SPI3;
op_finished_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
......
hdl/spi_master_multifield/test/spi_analyser.vhd
View file @ ceebd503
......@@ -58,6 +58,7 @@ architecture Behavioral of spi_analyser is
signal s_SPI0 : r_SPI0;
signal s_SPI1 : r_SPI1;
signal s_SPI1_tmp : r_SPI1;
signal s_spi_mosi : STD_LOGIC;
signal s_spi_clk : STD_LOGIC;
......@@ -73,8 +74,6 @@ architecture Behavioral of spi_analyser is
begin
s_SPI0 <= SPI0_i;
s_SPI1 <= SPI1_i;
s_spi_mosi <= spi_mosi_o;
s_spi_clk <= spi_clk_o;
......@@ -87,6 +86,15 @@ begin
end_addr_flag_o <= s_end_addr_flag;
end_data_flag_o <= s_end_data_flag;
s_SPI1_tmp <= SPI1_i;
p_latch : process (s_SPI1_tmp.SEND_OP)
begin
if rising_edge(s_SPI1_tmp.SEND_OP) then
s_SPI0 <= SPI0_i;
s_SPI1 <= SPI1_i;
end if;
end process;
p_spi_analyser: process(spi_clk_o, rst_i)
variable v_inst_length : NATURAL;
......
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