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C
Conv TTL Blocking
Commit d8b6d3c2 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Getting close to final version of UG

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doc/ug/fig/conv-sys-bd.svg
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doc/ug/ug-conv-ttl-blo.bib
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......@@ -35,3 +35,14 @@
title = {{White Rabbit}},
howpublished = {\url{http://www.ohwr.org/projects/white-rabbit}}
}
@misc{ohwr,
title = {{Conv TTL Blocking webpage on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo}}
}
@misc{sch,
title = {{CONV-TTL-BLO Schematics}},
howpublished = {\url{https://edms.cern.ch/file/1278535/1/EDA-02446-V2-1_sch.pdf}}
}
doc/ug/ug-conv-ttl-blo.tex
View file @ d8b6d3c2
......@@ -42,6 +42,8 @@ BE-CO-HT\\
\thispagestyle{empty}
\section*{Revision history}
\LARGE{\textcolor{red}{CHANGE ME!!}}
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
......@@ -65,14 +67,14 @@ BE-CO-HT\\
\listoffigures
\listoftables
\section*{List of abbreviations}
\section*{List of Abbreviations}
\begin{tabular}{l l}
\textit{FPGA} & Field-Programmable Gate Array \\
\textit{I$^2$C} & Inter-Integrated Circuit \\
\textit{PG} & Pulse Generator \\
\textit{RTM} & Rear Transition Module \\
\textit{SFP} & Small Form-factor Pluggable (connector) \\
\textit{VME} & VERSAmodule Eurocard \\
FPGA & Field-Programmable Gate Array \\
I$^2$C & Inter-Integrated Circuit \\
PG & Pulse Generator \\
RTM & Rear Transition Module \\
SFP & Small Form-factor Pluggable (connector) \\
VME & VERSAmodule Eurocard \\
\end{tabular}
%======================================================================================
......@@ -90,15 +92,15 @@ features of the board are:
\begin{itemize}
\item VME64x form-factor
\item Six independent pulse replication channels
\item Six independent pulse replication channels, each channel capable of replicating
\begin{itemize}
\item TTL to TTL
\item TTL-BAR to TTL-BAR
\item TTL to blocking
\item TTL-BAR to blocking
\item Blocking to TTL
\item Blocking to TTL-BAR
\item Blocking to blocking
\item TTL to TTL
\item TTL-BAR to TTL-BAR
\end{itemize}
\item Four general-purpose inverter channels
\item SFP connector for White Rabbit \cite{white-rabbit}
......@@ -109,7 +111,7 @@ features of the board are:
\begin{figure}[htbp]
\centerline{\includegraphics[width=\textwidth, keepaspectratio]{fig/conv-sys-bd}}
\caption{Symplified block diagram of the pulse conversion system}
\caption{Simplified block diagram of the pulse conversion system}
\label{fig:conv-sys-bd}
\end{figure}
......@@ -118,13 +120,17 @@ TTL-BAR pulse repeater using the six replication channels, or as a TTL to TTL-BA
(TTL-BAR to TTL) converter using the four general-purpose inverter channels.
By combining the CONV-TTL-BLO with the CONV-TTL-RTM rear-transition module (RTM) and the associated
CONV-TTL-BLO-RTM piggyback board in the rear part of the VME crate, a flexible six-channel pulse
CONV-TTL-RTM-BLO piggyback board in the rear part of the VME crate, a flexible six-channel pulse
conversion system can be obtained. Such a system is shown in Figure~\ref{fig:conv-sys-bd}.
TTL pulses arriving on an input TTL channel are regenerated in the FPGA and sent on the channel's
TTL output, as well as on the three blocking outputs on the RTM. Similarly, blocking
pulses arriving on a blocking input channel are regenerated in the FPGA and replicated
on both the TTL and blocking outputs of the channel.
CONV-TTL-BLO contains all active circuitry in a pulse conversion system. It handles
pulse generation and conversion from/to blocking. CONV-TTL-RTM is a passive module used
as an interface from the rear part of the VME crate to the front module.
%======================================================================================
% SEC: Panels
%======================================================================================
......@@ -150,7 +156,7 @@ of status LEDs and several ports; these are, from top to bottom:
\item System status LEDs;
\item Small form-factor pluggable (SFP) connector;
\item TTL pulse connectors and associated pulse LEDs;
\item TTL-BAR pulse connectors.
\item General-purpose inverter channels.
\end{itemize}
\begin{figure}[htbp]
......@@ -161,9 +167,9 @@ of status LEDs and several ports; these are, from top to bottom:
%--------------------------------------------------------------------------------------
\subsubsection{System status LEDs}
There are twelve bicolor status LEDs on the CONV-TTL-BLO front panel. Based on control signals
from the FPGA these LEDs can light red, green and orange. The implemented status LEDs are presented
in Table \ref{tbl:status-leds}. Unimplemented system status LEDs are \textit{off}.
There are twelve bicolor status LEDs on the CONV-TTL-BLO front panel. The implemented
status LEDs are presented in Table \ref{tbl:status-leds}. Unimplemented system status
LEDs are \textit{off}.
\begin{table}[h]
\caption{System status LEDs on CONV-TTL-BLO front panels}
......@@ -179,10 +185,11 @@ in Table \ref{tbl:status-leds}. Unimplemented system status LEDs are \textit{off
\textit{ERR} & Error LED. Lights \textit{red} when no RTM board is present, \textit{off} if a
valid RTM is present. \\
\textit{TTL} & TTL status LED. Lights \textit{green} when TTL logic is selected
via the on-board selection switch, \textit{off} otherwise. \\
\textit{I2C} & I$^2$C status LED, flashes \textit{green} when an I$^2$C transfer is taking place,
\textit{off} otherwise. Lights \textit{red} when a transfer error occurs, or when
the CONV-TTL-BLO register being addressed does not exist. \\
via the on-board selection switch, \textit{off} when TTL-BAR logic is selected. \\
\textit{I2C} & I$^2$C status LED. Flashes \textit{green} when an I$^2$C transfer is taking place.
Lights \textit{red} when a transfer error occurs, or when the CONV-TTL-BLO register
being addressed does not exist. Turns \textit{off} after a successful transfer has
ended.\\
\hline
\end{tabular}
}
......@@ -199,18 +206,17 @@ White Rabbit is currently not supported by the FPGA firmware.
%--------------------------------------------------------------------------------------
\subsubsection{TTL inputs and outputs}
Six of the LEMO 00 (type EPY) connectors on the CONV-TTL-BLO board are TTL repeater
Six of the LEMO 00 connectors on the CONV-TTL-BLO board are TTL repeater
channels. Both front-panel inputs and outputs are TTL-level (0-3.3~V). The signal
type and the inputs and outputs can be either TTL or TTL-BAR, as selected by the
TTL switch (SW2.4, see Section~\ref{sec:pulse-ttl-vs-ttlbar}).
A simplified diagram of pulse repetition is shown in Figure~\ref{fig:ttl-chan};
more details about pulse repetition can be found in Section~\ref{sec:pulse-rep}.
If a TTL (TTL-BAR) pulse arrives on a channel input, it gets replicated on the output of the
same channel in TTL (TTL-BAR), as well as the blocking outputs of the same channel on the
rear panel, if a CONV-TTL-RTM board with an attached CONV-TTL-RTM-BLO is present.
Similarly, if a blocking pulse arrives on the back panel, it is replicated on the TTL
output channel.
A simplified diagram of pulse repetition is shown in Figure~\ref{fig:ttl-chan},
more details can be found in Section~\ref{sec:pulse-rep}. If a TTL (TTL-BAR) pulse arrives
on a channel input, it gets replicated on the output of the same channel in TTL (TTL-BAR),
as well as the blocking outputs of the same channel on the rear panel, if a CONV-TTL-RTM
board with an attached CONV-TTL-RTM-BLO is present. Similarly, if a blocking pulse arrives
on the back panel, it is replicated on the TTL output channel.
\begin{figure}[htbp]
\centerline{\includegraphics[scale=.75]{fig/ttl-chan}}
......@@ -221,19 +227,25 @@ output channel.
Each TTL replication channel has a pulse LED which flashes shortly whenever a pulse is replicated
on the channel.
All TTL input channels are line-terminated with 50$\Omega$ resistors; TTL output channels are
not line-terminated.
All TTL input channels are terminated with 50$\Omega$ resistors; TTL output channels are
not terminated.
%--------------------------------------------------------------------------------------
\subsubsection{General-purpose inverters}
Four general-purpose TTL inverter channels can be found in the lower part of the front panel.
The output of a channel is always an inverted version of the channel input. No regeneration
is performed on the input signal, nor is it in any way connected to the blocking outputs on
the RTM. The input signal is simply passed through an inverter and presented at the channel
output (see Figure~\ref{fig:conv-sys-bd}).
The output of a channel is always an inverted version of the channel input (Figure~\ref{fig:invttl-chan}).
No regeneration is performed on the input signal, nor is it in any way connected to the blocking outputs
on the RTM. The input signal is simply passed through an inverter and presented at the
channel output (see Figure~\ref{fig:conv-sys-bd}).
All general-purpose inputs are internally terminated with 50$\Omega$ resistors; the outputs
are not internally terminated.
\begin{figure}[h]
\centerline{\includegraphics[scale=.85]{fig/invttl-chan}}
\caption{TTL general-purpose inverter channel}
\label{fig:invttl-chan}
\end{figure}
All general-purpose inputs are terminated with 50$\Omega$ resistors; the outputs are not
terminated.
%--------------------------------------------------------------------------------------
% SUBSEC: Rear panel
......@@ -246,7 +258,7 @@ pulse at the input connector of a channel is repeated at the three outputs of th
blocking level and in TTL level at the output connector of the corresponding TTL channel on the front panel.
All blocking input channels have internal line-termination with 50$\Omega$ resistors. Blocking outputs are
not line-terminated. Each output on a channel has its separate blocking driver.
not line-terminated. Each output on a channel has a separate blocking driver.
When a pulse is repeated on the output connector of a channel, the pulse status LED flashes briefly.
......@@ -265,10 +277,8 @@ When a pulse is repeated on the output connector of a channel, the pulse status
\section{On-board switches}
\label{sec:switches}
There are eight switches provided on-board the CONV-TTL-BLO board. This section provides
a summary on the switches, more details can be found in following sections.
Figure~\ref{fig:switches} shows the switches on board and Table~\ref{tbl:switches}
lists the usable switches.
There are eight switches provided on-board the CONV-TTL-BLO board, shown in
Figure~\ref{fig:switches}. Table~\ref{tbl:switches} lists the used switches.
\begin{figure}[htbp]
\centerline{\includegraphics[scale=.75]{fig/switches}}
......@@ -296,33 +306,27 @@ lists the usable switches.
}
\end{table}
SW1.1 (Section~\ref{sec:pulse-rep}) is used to select whether the pulse generated at
the output should have jitter or not. Based on application and the environment in which
the boards are used, the generated pulse can be either jitter-free, or glitch-filtered.
Setting SW1.1 in the \textbf{OFF} position yields jitter-free pulses that can be used
when the environment is not noisy and pulse jitter is an issue. In these cases, the
signal generated at the output has no output jitter, but can be sensitive to glitches,
i.e., a glitch at the input may trigger the generation of a pulse.
When the environment is noisy and pulse jitter is not a major issue, SW1.1 can be set
in the \textbf{ON} position, pulses narrower than 40~ns are not replicated at the output.
Pulses longer than 40~ns are replicated at the output and present an 8~ns jitter at the
leading edge (see Figure~\ref{fig:jitter}).
\begin{figure}[htbp]
\centerline{\includegraphics[scale=1]{fig/jitter}}
\caption{Output pulse jitter}
\label{fig:jitter}
\end{figure}
%SW1.1 (Section~\ref{sec:pulse-rep}) is used to select whether the pulse generated at
%the output should have jitter or not. Based on application and the environment in which
%the boards are used, the generated pulse can be either jitter-free, or glitch-filtered.
%
%Setting SW1.1 in the \textbf{OFF} position yields jitter-free pulses that can be used
%when the environment is not noisy and pulse jitter is an issue. In these cases, the
%signal generated at the output has no output jitter, but can be sensitive to glitches,
%i.e., a glitch at the input may trigger the generation of a pulse.
%
%When the environment is noisy and pulse jitter is not a major issue, SW1.1 can be set
%in the \textbf{ON} position, pulses narrower than 40~ns are not replicated at the output.
%Pulses longer than 40~ns are replicated at the output and present an 8~ns jitter at the
%leading edge (see Figure~\ref{fig:jitter}).
SW2.4 (Section~\ref{sec:pulse-ttl-vs-ttlbar}) is used to select whether TTL or TTL-BAR
signals are are input and output on the front panel TTL repetition channels.
%SW2.4 (Section~\ref{sec:pulse-ttl-vs-ttlbar}) is used to select whether TTL or TTL-BAR
%signals are are input and output on the front panel TTL repetition channels.
Note that both switches are board-wide switches; selecting one position or the other
yields a selection valid for all six pulse replication channels.
The default position of the switches \textbf{OFF}.
The default position of the switches is \textbf{OFF}.
%======================================================================================
% SEC: Pulse replication
......@@ -341,9 +345,7 @@ Three pulse types are defined in the context of CONV-TTL-BLO, depending on signa
rise and fall times; pulse widths and frequencies are the same. TTL and TTL-BAR pulses
are input and output on the front panel of the boards. TTL-BAR is essentially an inverted
version of TTL signals. Blocking pulses \cite{StandardBlocking} are input and output on the
ear panel (via a CONV-TTL-RTM). The various characteristics of the pulse signals are defined
in Figure~\ref{fig:pulse-def} and outlined in Table~\ref{tbl:pulse-def} per each signal
type.
ear panel (via a CONV-TTL-RTM).
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-def}}
......@@ -352,29 +354,65 @@ type.
\end{figure}
\begin{table}[h]
\caption{Pulse characteristics}
\label{tbl:pulse-def}
\caption{TTL and TTL-BAR pulse characteristics}
\label{tbl:pulse-def-ttl}
\centerline
{
\begin{tabular}{l l c c c c}
\hline
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
\textbf{TTL} & \textbf{Blocking} & \textbf{Unit} \\
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
\textbf{Min.} & \textbf{Typ.} & \textbf{Max.} & \textbf{Unit}\\
\hline
$V_{p,max}$ & Pulse max. amplitude & 3.3 & 24 & V \\
$V_{p,min}$ & Pulse min. amplitude (1) & 0.5 & 4.5 & V \\
$t_p$ & Pulse width & 1.2 & 1.2 & $\mu$s \\
$T_{min}$ & Min. period of pulse signal (2) & 4.8 & 4.8 & $\mu$s \\
$t_r$ & Rise time & 6.4 & 140 & ns \\
$t_f$ & Fall time & 3 & 160 & ns \\
$V_{IH}$ & Input pulse high-level amplitude (1) & 1 & & 5.5 & V \\
$V_{IL}$ & Input pulse low-level amplitude & & 0 & & V \\
$V_{OH}$ & Output pulse high-level amplitude & & 3.3 & & V \\
$V_{OL}$ & Output pulse low-level amplitude & & 0 & & V \\
$t_p$ & Pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (2) & 4.8 & & & ${\mu}s$ \\
$t_r$ & Rise time & & 6.4 & & ns \\
$t_f$ & Fall time & & 3 & & ns \\
\hline
\end{tabular}
}
\end{table}
\noindent Note 0: All voltages referred from 0~V. \\
\noindent Note 1: Min. pulse amplitude for which a pulse is replicated at the output. \\
\noindent Note 1: Min. pulse amplitude for which a $t_p$ wide pulse is replicated at the output. \\
\noindent Note 2: Max. pulse frequency dictated by blocking output max. frequency. \\
\noindent All voltages are referred from 0~V; unless otherwise noted, all values are
typical values. \\
The various characteristics of the pulse signals are defined in
Figure~\ref{fig:pulse-def} and outlined in Table~\ref{tbl:pulse-def-ttl} for
TTL and TTL-BAR pulses, and in Table~\ref{tbl:pulse-def-blo} for blocking
pulses.
\begin{table}[h]
\caption{Blocking pulse characteristics}
\label{tbl:pulse-def-blo}
\centerline
{
\begin{tabular}{l l c c c c}
\hline
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
\textbf{Min.} & \textbf{Typ.} & \textbf{Max.} & \textbf{Unit}\\
\hline
$V_{IH}$ & Input pulse high-level amplitude (1) & 3.7 & & & V \\
$V_{IL}$ & Input pulse low-level amplitude & & 0 & & V \\
$V_{OH}$ & Output pulse high-level amplitude & & 24 & & V \\
$V_{OL}$ & Output pulse low-level amplitude & & 0 & & V \\
$t_p$ & Pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Min. period of pulse signal (2) & 4.8 & 4.8 & & ${\mu}s$ \\
$t_r$ & Rise time & & 140 & & ns \\
$t_f$ & Fall time & & 160 & & ns \\
\hline
\end{tabular}
}
\end{table}
\noindent Note 1: Min. pulse amplitude for which a $t_p$ wide pulse is replicated at the output. \\
\noindent Note 2: Max. pulse frequency dictated by blocking output max. frequency. \\
\noindent All voltages are referred from 0~V; unless otherwise noted, all values are
typical values. \\
%--------------------------------------------------------------------------------------
% SUBSEC: TTL vs TTL-BAR
......@@ -452,6 +490,12 @@ for a continuous high level on the line. This is important when the TTL selectio
switch is set to TTL-BAR, since no signal would mean a DC high-level signal appears at the
OR gate input and this signal would inhibit pulses arriving from the blocking side.
%--------------------------------------------------------------------------------------
% SUBSEC: Rep details
%--------------------------------------------------------------------------------------
\subsection{Pulse jitter and delay}
\label{sec:pulse-jit}
As outlined in Section~\ref{sec:switches}, the PG block is capable of generating either
jitter-free, or glitch-filtered pulses. SW1.1 (Figure~\ref{fig:switches-ptype}) selects
between the two options.
......@@ -467,6 +511,12 @@ the pulse signal is replicated at the output without being sampled with an on-bo
clock. This however also means that any glitch pulse wider than 8~ns will trigger
pulse generation at the output.
\begin{figure}[htbp]
\centerline{\includegraphics[scale=1]{fig/jitter}}
\caption{Output pulse jitter}
\label{fig:jitter}
\end{figure}
Placing SW1.1 in the \textbf{ON} position will enable glitch filtering on the PG block.
The pulse signal is in this case sampled with a 125~MHz on-board clock and passed through a
glitch filter which rejects any pulses narrower than 40~ns, but introduces an 8~ns jitter at
......@@ -589,12 +639,15 @@ The memory map of registers accessible through the ELMA protocol is given in Tab
%======================================================================================
% Appendix: Getting started
% Appendices
%======================================================================================
\pagebreak
\begin{appendices}
%======================================================================================
% Appendix: Getting started
%======================================================================================
\section{Getting started with the CONV-TTL-BLO}
\label{sec:app-get-started}
......@@ -1097,6 +1150,9 @@ be followed in order to test the board.
% Bibliography
%======================================================================================
\pagebreak
% Make non-cited refs appear in references
\nocite{ohwr}
\nocite{sch}
\bibliographystyle{ieeetr}
\bibliography{ug-conv-ttl-blo}
......
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