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Conv TTL Blocking
Commit e2084caf authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Renamed pulse gens, redesigned CSR 

The CSR now has individual bits controlling pulse generation, LED
sequencing and setting the RTM blocking pulse LED lines for testing them
and the RTM detection lines.

The doc files for the PTS have also been moved to the main doc/ folder,
and work on pts_hdlguide has restarted.
parent 4c3d7df3
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Showing with 353 additions and 232 deletions
doc/pts/.gitignore 0 → 100644
View file @ e2084caf
build/
\ No newline at end of file
doc/pts/pts_hdlguide.bib 0 → 100644
View file @ e2084caf
@misc{StandardBlocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
@TECHREPORT{UG380,
institution = "Xilinx Inc.",
title = {{Spartan-6 FPGA Configuration User Guide}},
month = jul,
year = 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
@misc{rtm-ident,
title = {{RTM detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
@misc{flyback,
title = {{Under the Hood of Flyback SMPS Designs}},
howpublished = {\url{http://focus.ti.com/asia/download/Topic_1_Picard_42pages.pdf}}
}
doc/pts/pts_hdlguide.tex 0 → 100644
View file @ e2084caf
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{color}
\begin{document}
\title{
\textbf{
Conv-TTL-Blo Production Test Suite\\
HDL Developer's Guide\\}}
\author{Theodor-Adrian Stana\\
% \href{mailto:t.stana@cern.ch}{\textbf{\textit{t.stana@cern.ch}}}\\
BE-CO-HT\\
}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{fig/cern-logo.png}
\end{center}
\end{figure}
\maketitle{}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
\pagebreak
\listoffigures
\listoftables
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\thispagestyle{empty}
\section*{List of abbreviations}
\begin{tabular}{l l}
\textit{FPGA} & Field-Programmable Gate Array \\
\textit{PTS} & Production Test Suite \\
\textit{RTM} & Rear Transition Module \\
\textit{RTMM} & RTM Motherboard \\
\textit{RTMP} & RTM Piggyback \\
\textit{SFP} & Small form-factor pluggable (in the context of SFP connectors) \\
\end{tabular}
%======================================================================================
% SEC: Intro
%======================================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
This document presents a high-level view of the firmware implemented on the FPGA for the
Production Test Suite (PTS) project for the Conv-TTL-Blo board. The document starts with a
description of the folder structure and where the developer should look for specific files.
In the following section, the structure of the top-level HDL file is given along with
hints on where the developer should look in case changes are to be made
to the code. After that, the memory map is presented, followed by sections
describing the logic implemented to run the tests comprising PTS.
All the logic implemented on the FPGA is written in VHDL and can be obtained freely by cloning
the OHWR git repository for the Conv-TTL-Blo PTS project at the following link:
\textcolor{red}{link ohwr repo}
\textcolor{red}{\cite{StandardBlocking}}
\textcolor{red}{REFERENCE THE OTHER DOCUMENTS}
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{pts_hdlguide}
\end{document}
hdl/pulse_generator/rtl/Manifest.py → hdl/ctb_pulse_gen/rtl/Manifest.py
View file @ e2084caf
files = "pulse_generator.vhd"
files = "ctb_pulse_gen.vhd"
modules = {
"local" : [
......
hdl/pulse_generator/rtl/pulse_generator.vhd → hdl/ctb_pulse_gen/rtl/ctb_pulse_gen.vhd
View file @ e2084caf
......@@ -56,7 +56,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_generator is
entity ctb_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
......@@ -92,10 +92,10 @@ entity pulse_generator is
-- TYPE 2 pulse: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
);
end entity pulse_generator;
end entity ctb_pulse_gen;
architecture behav of pulse_generator is
architecture behav of ctb_pulse_gen is
--============================================================================
-- Type declarations
......
hdl/pulse_gen/rtl/pulse_gen.vhd → hdl/ctb_pulse_gen_gp/rtl/ctb_pulse_gen_gp.vhd
View file @ e2084caf
......@@ -39,7 +39,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen is
entity ctb_pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
......@@ -53,10 +53,10 @@ entity pulse_gen is
en_i : in std_logic;
pulse_o : out std_logic
);
end entity pulse_gen;
end entity ctb_pulse_gen_gp;
architecture behav of pulse_gen is
architecture behav of ctb_pulse_gen_gp is
--============================================================================
-- Function and procedure declarations
......
hdl/pts/rtl/pts_regs.vhd
View file @ e2084caf
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Fri May 3 17:05:11 2013
-- Created : Wed May 29 11:50:18 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
......@@ -27,8 +27,16 @@ entity pts_regs is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'current test' in reg: 'control and status register'
pts_csr_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for BIT field: 'TTL pulse enable' in reg: 'control and status register'
pts_csr_ttl_en_o : out std_logic;
-- Port for BIT field: 'Blocking pulse enable' in reg: 'control and status register'
pts_csr_blo_en_o : out std_logic;
-- Port for BIT field: 'Blocking LED control' in reg: 'control and status register'
pts_csr_blo_led_o : out std_logic;
-- Port for BIT field: 'pulse LED enable' in reg: 'control and status register'
pts_csr_pulse_led_en_o : out std_logic;
-- Port for BIT field: 'status LED enable' in reg: 'control and status register'
pts_csr_stat_led_en_o : out std_logic;
-- Port for BIT field: 'reset' in reg: 'control and status register'
pts_csr_rst_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'control and status register'
......@@ -42,7 +50,11 @@ end pts_regs;
architecture syn of pts_regs is
signal pts_csr_crrt_test_int : std_logic_vector(3 downto 0);
signal pts_csr_ttl_en_int : std_logic ;
signal pts_csr_blo_en_int : std_logic ;
signal pts_csr_blo_led_int : std_logic ;
signal pts_csr_pulse_led_en_int : std_logic ;
signal pts_csr_stat_led_en_int : std_logic ;
signal pts_csr_rst_int : std_logic ;
signal pts_id_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
......@@ -72,9 +84,13 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pts_csr_crrt_test_int <= "0000";
pts_csr_ttl_en_int <= '0';
pts_csr_blo_en_int <= '0';
pts_csr_blo_led_int <= '0';
pts_csr_pulse_led_en_int <= '0';
pts_csr_stat_led_en_int <= '0';
pts_csr_rst_int <= '0';
pts_id_bits_int <= x"424C4F32";
pts_id_bits_int <= x"424c4f32";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -89,14 +105,21 @@ begin
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
pts_csr_crrt_test_int <= wrdata_reg(3 downto 0);
pts_csr_ttl_en_int <= wrdata_reg(0);
pts_csr_blo_en_int <= wrdata_reg(1);
pts_csr_blo_led_int <= wrdata_reg(2);
pts_csr_pulse_led_en_int <= wrdata_reg(3);
pts_csr_stat_led_en_int <= wrdata_reg(4);
pts_csr_rst_int <= wrdata_reg(15);
end if;
rddata_reg(3 downto 0) <= pts_csr_crrt_test_int;
rddata_reg(0) <= pts_csr_ttl_en_int;
rddata_reg(1) <= pts_csr_blo_en_int;
rddata_reg(2) <= pts_csr_blo_led_int;
rddata_reg(3) <= pts_csr_pulse_led_en_int;
rddata_reg(4) <= pts_csr_stat_led_en_int;
rddata_reg(15) <= pts_csr_rst_int;
rddata_reg(23 downto 16) <= pts_csr_switch_i;
rddata_reg(29 downto 24) <= pts_csr_rtm_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -131,8 +154,16 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- current test
pts_csr_crrt_test_o <= pts_csr_crrt_test_int;
-- TTL pulse enable
pts_csr_ttl_en_o <= pts_csr_ttl_en_int;
-- Blocking pulse enable
pts_csr_blo_en_o <= pts_csr_blo_en_int;
-- Blocking LED control
pts_csr_blo_led_o <= pts_csr_blo_led_int;
-- pulse LED enable
pts_csr_pulse_led_en_o <= pts_csr_pulse_led_en_int;
-- status LED enable
pts_csr_stat_led_en_o <= pts_csr_stat_led_en_int;
-- reset
pts_csr_rst_o <= pts_csr_rst_int;
-- switches
......
hdl/pts/rtl/pts_regs.wb
View file @ e2084caf
......@@ -7,14 +7,47 @@ peripheral {
reg {
name = "control and status register";
prefix = "csr";
field {
name = "current test";
prefix = "crrt_test";
type = SLV;
size = 4;
name = "TTL pulse enable";
prefix = "ttl_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Blocking pulse enable";
prefix = "blo_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Blocking LED control";
prefix = "blo_led";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "pulse LED enable";
prefix = "pulse_led_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "status LED enable";
prefix = "stat_led_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "reset";
prefix = "rst";
......@@ -23,6 +56,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "switches";
prefix = "switch";
......@@ -32,6 +66,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RTM";
prefix = "rtm";
......
hdl/pts/syn/Makefile
View file @ e2084caf
......@@ -134,8 +134,8 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../pulse_gen/rtl/pulse_gen.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../ctb_pulse_gen_gp/rtl/ctb_pulse_gen_gp.vhd \
../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
../../vme64x_i2c/rtl/i2c_slave.vhd \
......
hdl/pts/syn/conv_ttl_blo_v2.gise
View file @ e2084caf
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807798" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807863" xil_pn:in_ck="2106099442498953536" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1368807798">
<transform xil_pn:end_ts="1369821184" xil_pn:in_ck="8612814983564804210" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1369821120">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1368807863" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1368807863">
<transform xil_pn:end_ts="1369821184" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1369821184">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368807876" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1368807863">
<transform xil_pn:end_ts="1369821198" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1369821184">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1368808087" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1368807876">
<transform xil_pn:end_ts="1369821449" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1369821198">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -145,7 +145,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1368808177" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1368808087">
<transform xil_pn:end_ts="1369821553" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1369821449">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -159,7 +159,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1368808215" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1368808177">
<transform xil_pn:end_ts="1369821592" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1369821553">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -171,7 +171,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1368808177" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1368808160">
<transform xil_pn:end_ts="1369821553" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1369821536">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/pts/syn/conv_ttl_blo_v2.xise
View file @ e2084caf
......@@ -362,16 +362,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../rtl/pts_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../rtl/pulse_cnt_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../rtl/clk_info_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
......@@ -643,11 +643,11 @@
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../pulse_gen/rtl/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
<file xil_pn:name="../../ctb_pulse_gen_gp/rtl/ctb_pulse_gen_gp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../pulse_generator/rtl/pulse_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
<file xil_pn:name="../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
......
hdl/pts/top/Manifest.py
View file @ e2084caf
......@@ -7,8 +7,8 @@ modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../pulse_gen",
"../../pulse_generator",
"../../ctb_pulse_gen_gp",
"../../ctb_pulse_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../../vme64x_i2c",
......
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @ e2084caf
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