Commit ee3b4c61 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

test00 & test07 complete

parent df053143
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target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo_v2"
syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../top"
]
}
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PROMGEN: Xilinx Prom Generator P.28xd
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
promgen -spi -w -u 0 conv_ttl_blo_v2.bit
PROM conv_ttl_blo_v2.prm map: Wed Mar 27 16:36:24 2013
Format Mcs86 (32-bit)
Size 2048K
PROM start 0000:0000
PROM end 001f:ffff
Addr1 Addr2 Date File(s)
0000:0000 0016:a673 Mar 27 14:19:40 2013 conv_ttl_blo_v2.bit
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project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
files = [
"conv_ttl_blo_v2.ucf",
"pts_regs.vhd",
"conv_ttl_blo_v2.vhd"
]
modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../../vme64x_i2c"
]
}
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for PTS registers
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Wed Mar 27 17:33:09 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pts_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'current test' in reg: 'control register'
pts_ctrl_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 't00'
pts_t00_bits_o : out std_logic_vector(31 downto 0)
);
end pts_regs;
architecture syn of pts_regs is
signal pts_ctrl_crrt_test_int : std_logic_vector(3 downto 0);
signal pts_t00_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pts_ctrl_crrt_test_int <= "0000";
pts_t00_bits_int <= x"424C4F32";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
pts_ctrl_crrt_test_int <= wrdata_reg(3 downto 0);
end if;
rddata_reg(3 downto 0) <= pts_ctrl_crrt_test_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
pts_t00_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pts_t00_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- current test
pts_ctrl_crrt_test_o <= pts_ctrl_crrt_test_int;
-- bits
pts_t00_bits_o <= pts_t00_bits_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
peripheral {
name = "PTS registers";
description = "Registers of the PTS firmware";
hdl_entity = "pts_regs";
prefix = "pts";
reg {
name = "control register";
prefix = "ctrl";
field {
name = "current test";
prefix = "crrt_test";
type = SLV;
size = 4;
};
};
reg {
name = "t00";
prefix = "t00";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
};
modules = {"local" : "rtl"}
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