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Conv TTL Blocking
Commit f03f5447 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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I2C slave working, with ELMA protocol on top. Submitting last changes + doc for… 

I2C slave working, with ELMA protocol on top. Submitting last changes + doc for I2C slave. Also updated order-record doc
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doc/ug/ug-conv-ttl-blo.tex
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%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
% \usepackage{draftwatermark}
% \SetWatermarkLightness{0.90}
% \SetWatermarkScale{5}
%\usepackage{float}
%\restylefloat{table}
\usepackage{color}
......
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build/
fig/
*.tex
*.bib
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FILE=i2c_slave
all:
pdflatex -synctex=1 -interaction=nonstopmode *.tex
bibtex *.aux
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode *.tex
evince $(FILE).pdf &
clean:
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
hdl/vme64x_i2c/doc/i2cSpecs.tex deleted 100644 → 0
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hdl/vme64x_i2c/rtl/bridge.vhd deleted 100644 → 0
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hdl/vme64x_i2c/rtl/bridge_regs.vhd deleted 100644 → 0
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hdl/vme64x_i2c/rtl/i2c_bit.vhd deleted 100644 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the fsm for the recognition of a bit. It offers some
-- interrupting lines to the upper level (i2c_slave_core.vhd)
-- which is responsible for managing byte level transactions
--
-- Dependencies: The inputs should be debounced: i2c_debouncer.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- 0.1 - Module works with no reported issues.
-- 1.0 - Code revamped. Now is clearer and easier to read.
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_bit is
port
(
rst_i : in std_logic;
clk_i : in std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
tx_i : in std_logic;
rx_o : out std_logic;
start_o : out std_logic;
stop_o : out std_logic;
done_o : out std_logic
);
end entity i2c_bit;
architecture behav of i2c_bit is
component i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic;
glitch_mask : in std_logic_VECTOR(g_LENGTH - 1 downto 0)
);
end component i2c_debouncer;
type t_state is (
R0_RESET,
S0_IDLE,
S1A_HIGH_TMP,
S1A_HIGH,
S1B_LOW_TMP,
S1B_LOW,
S2A_START_TMP,
S2A_START,
S2B_STOP_DETECT,
Q1_ERROR
);
-- It specifies the maximum number of stages that will be employed for
-- deglitching. Clocked with clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
-- Three delay stages out of six
constant c_GLITCH_MASK : std_logic_VECTOR (5 downto 0) := "000111";
signal sda_degl : std_logic;
signal sda_degl_d0 : std_logic;
signal scl_degl : std_logic;
signal scl_degl_d0 : std_logic;
signal state : t_state;
signal scl_rising : std_logic;
signal scl_falling : std_logic;
begin
cmp_scl_debouncer: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => clk_i,
input => scl_i,
output => scl_degl,
glitch_mask => c_GLITCH_MASK
);
cmp_sda_debounce: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => clk_i,
input => sda_i,
output => sda_degl,
glitch_mask => c_GLITCH_MASK
);
p_degl_delay: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
sda_degl_d0 <= '0';
scl_degl_d0 <= '0';
else
sda_degl_d0 <= sda_degl;
scl_degl_d0 <= scl_degl;
end if;
end if;
end process p_degl_delay;
p_fsm: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
state <= ST_IDLE;
start_o <= '0';
stop_o <= '0';
rcved_o <= '0';
done_o <= '0';
else
case state is
when ST_IDLE =>
when others =>
end case;
end if;
end if;
end process p_fsm;
-- -- This is the process that samples the scl for detecting
-- -- rise and falling edges
-- reg_proc: process (clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- scl_falling <= '0';
-- scl_rising <= '0';
-- elsif (scl_degl = '0') and (scl_degl_d0 = '1') then
-- scl_falling <= '1';
-- elsif (scl_degl = '1') and (scl_degl_d0 = '0') then
-- scl_rising <= '1';
-- else
-- scl_falling <= '0';
-- scl_rising <= '0';
-- end if;
-- end if;
-- end process;
-- -- Combinatorial process to update the outputs.
-- p_comb_output: process(state)
-- begin
-- start_o <= '0';
-- stop_o <= '0';
-- rcved_o <= '0';
-- done_o <= '0';
--
-- case state is
--
-- when R0_RESET =>
-- null;
--
-- when S0_IDLE =>
-- null;
--
-- when S1A_HIGH =>
-- rcved_o <= '1';
-- done_o <= '1';
--
-- when S1B_LOW =>
-- rcved_o <= '0';
-- done_o <= '1';
--
-- when S2A_START =>
-- start_o <= '1';
-- done_o <= '1';
--
-- when S2B_STOP_DETECT =>
-- stop_o <= '1';
-- done_o <= '1';
--
-- when Q1_ERROR =>
-- null;
--
-- when others =>
-- null;
--
-- end case;
-- end process p_comb_output;
-- -- The fsm of this module, later on the sda sampled line is
-- -- validated in the falling edge of scl.
-- p_fsm: process(clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- state <= R0_RESET;
-- elsif scl_falling = '1' then
-- -- After a detection of a falling edge we update the
-- -- detection of a '0', a '1' and a start condition.
-- case state is
-- when S1A_HIGH_TMP =>
-- state <= S1A_HIGH;
--
-- when S1B_LOW_TMP =>
-- state <= S1B_LOW;
--
-- when S2A_START_TMP =>
-- state <= S2A_START;
--
-- when others =>
-- state <= S0_IDLE;
-- end case;
--
-- elsif (scl_rising = '1') then
-- -- When a rising edge is detected we annotate the first value
-- -- in SDA: either a temporary '0' or '1'
-- if (sda_degl_d0 = '1') then
-- state <= S1A_HIGH_TMP;
-- else
-- state <= S1B_LOW_TMP;
-- end if;
--
-- else
-- -- When we are in high level of a scl cycle, we keep on updating
-- -- the FSM
-- if (scl_degl = '1') then
-- case state is
-- -- Just for random bit swapped coverage.
-- when S0_IDLE =>
-- if (sda_degl = '1') then
-- state <= S1A_HIGH_TMP;
-- else
-- state <= S1B_LOW_TMP;
-- end if;
--
-- when S1A_HIGH_TMP =>
-- if sda_degl = '0' then
-- -- The detection of the start condition will be reported
-- -- in the next SCL rising edge.
-- state <= S2A_START_TMP;
-- end if;
--
-- when S1B_LOW_TMP =>
-- if sda_degl = '1' then
-- -- The detection of the pause condition MUST be
-- -- reported immediately.
-- state <= S2B_STOP_DETECT;
-- end if;
--
-- when S2A_START_TMP =>
-- if (sda_degl = '1') then
-- --! This happens if the deglitching is not enough
-- state <= Q1_ERROR;
-- end if;
--
-- when others =>
-- state <= S0_IDLE;
-- end case;
-- else
-- if (scl_degl_d0 = '0') then
-- state <= S0_IDLE;
-- end if;
-- end if;
-- end if;
-- end if;
-- end process p_fsm;
end behav;
hdl/vme64x_i2c/rtl/i2c_debounce.vhd deleted 100644 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:11:43 10/25/2011
-- Design Name:
-- Module Name: i2c_debounce - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a I2C debouncer. The main difference is that it is
-- intended to filter out low glitches. That means the oppositive
-- from the previous version --debouncer.vhd.
-- This behaviour makes more sense compared on how I2C definition
-- resolves arbitration --conceptually the same as this module.
--
-- A '1' in the glitch_mask means that the bit should be studied.
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
signal input_d0 : STD_LOGIC;
-- The first of this signal is already stable (ff'ed two times at [0])
signal delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
input_d0 <= '0';
delay <= (others => '0');
else
input_d0 <= input;
delay(0) <= input_d0;
delay(g_length-1 downto 1) <= delay(g_length-2 downto 0);
end if;
end if;
end process;
p_output: process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
output <= '1';
else
-- We can deglitch either zeros or ones
if ( (delay and glitch_mask) = glitch_mask
or (not(delay) and glitch_mask) = glitch_mask) then
output <= delay(0);
else
-- Internall pull-up of the pin
output <= '1';
end if;
end if;
end if;
end process p_output;
end Behavioral;
hdl/vme64x_i2c/rtl/i2c_slave.vhd
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hdl/vme64x_i2c/rtl/i2c_slave_pkg.vhd deleted 100644 → 0
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hdl/vme64x_i2c/rtl/vme64x_i2c.vhd
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hdl/vme64x_i2c/sim/run.do
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......@@ -14,5 +14,5 @@ radix -hexadecimal
# add wave *
do wave.do
run 3 ms
run 4 ms
wave zoomfull
hdl/vme64x_i2c/sim/tb_vme64x_i2c.vhd
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......@@ -306,8 +306,8 @@ begin
);
-- BUS MODEL
scl_to_mst <= scl_fr_mst when scl_en_mst = '0' else
scl_fr_slv when scl_en_slv = '1' else
scl_to_mst <= scl_fr_slv when scl_en_slv = '1' else
scl_fr_mst when scl_en_mst = '0' else
'1';
sda_to_mst <= sda_fr_slv when sda_en_slv = '1' else
sda_fr_mst when sda_en_mst = '0' else
......@@ -316,10 +316,11 @@ begin
scl_to_slv <= scl_fr_mst when scl_en_mst = '0' else
scl_fr_slv when scl_en_slv = '1' else
'1';
sda_to_slv <= sda_fr_slv when sda_en_slv = '1' else
sda_fr_mst when sda_en_mst = '0' else
sda_to_slv <= sda_fr_mst when sda_en_mst = '0' else
sda_fr_slv when sda_en_slv = '1' else
'1';
-- STIMULI
-- ADDRESS
i2c_addr <= "1011110";
-- I2C MASTER FSM
......@@ -433,9 +434,19 @@ begin
when ST_RD =>
mst_rd <= '1';
mst_ack <= '0';
if (byte_cnt = 3) then
mst_ack <= '1';
end if;
if (mst_cmd_ack = '1') then
mst_rd <= '0';
state <= ST_RD_WA;
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state <= ST_RD;
if (byte_cnt = 3) then
state <= ST_STO;
end if;
end if;
when ST_RD_WA =>
......@@ -443,9 +454,9 @@ begin
if (cnt = 7) then
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state <= ST_RD;
if (byte_cnt = 3) then
read4 <= '1';
state <= ST_STO;
end if;
end if;
......@@ -461,11 +472,15 @@ begin
when ST_WR_WA =>
cnt <= cnt + 1;
if (cnt = 7) then
byte_cnt <= byte_cnt + 1;
send <= x"00" & send(31 downto 8);
state <= ST_WR;
if (byte_cnt = 3) then
state <= ST_STO;
if (ack_fr_slv = '0') then
byte_cnt <= byte_cnt + 1;
send <= x"00" & send(31 downto 8);
state <= ST_WR;
if (byte_cnt = 3) then
state <= ST_STO;
end if;
else
state <= ST_ERR;
end if;
end if;
......@@ -476,12 +491,17 @@ begin
state <= ST_I2C_ADDR;
send <= x"44332211";
wrote <= '1';
slv_wb_adr <= x"0003";
if (wrote = '1') then
state <= ST_I2C_ADDR;
fsm_op <= '1';
--slv_wb_adr <= x"0004";
if (fsm_op = '1') then
state <= ST_SUCCESS;
read4 <= '1';
slv_wb_adr <= x"0001";
state <= ST_I2C_ADDR;
if (read4 = '1') then
state <= ST_SUCCESS;
end if;
end if;
end if;
end if;
......
hdl/vme64x_i2c/sim/transcript
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hdl/vme64x_i2c/sim/wave.do
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......@@ -17,13 +17,15 @@ add wave -noupdate /tb_vme64x_i2c/wb_dat_s2m
add wave -noupdate /tb_vme64x_i2c/wb_adr
add wave -noupdate /tb_vme64x_i2c/wb_ack
add wave -noupdate /tb_vme64x_i2c/state
add wave -noupdate /tb_vme64x_i2c/slv_wb_adr
add wave -noupdate /tb_vme64x_i2c/reg
add wave -noupdate /tb_vme64x_i2c/rcvd
add wave -noupdate /tb_vme64x_i2c/read4
add wave -noupdate /tb_vme64x_i2c/send
add wave -noupdate /tb_vme64x_i2c/wrote4
add wave -noupdate -divider dut
add wave -noupdate /tb_vme64x_i2c/DUT/state
add wave -noupdate /tb_vme64x_i2c/DUT/done
add wave -noupdate -radix binary /tb_vme64x_i2c/DUT/stat
add wave -noupdate /tb_vme64x_i2c/DUT/op
add wave -noupdate /tb_vme64x_i2c/DUT/start_op
add wave -noupdate /tb_vme64x_i2c/DUT/wb_dat_out
......@@ -36,8 +38,13 @@ add wave -noupdate /tb_vme64x_i2c/DUT/cmp_i2c_slave/state
add wave -noupdate /tb_vme64x_i2c/DUT/cmp_i2c_slave/txsr
add wave -noupdate /tb_vme64x_i2c/DUT/cmp_i2c_slave/rxsr
add wave -noupdate /tb_vme64x_i2c/DUT/cmp_i2c_slave/bit_cnt
add wave -noupdate /tb_vme64x_i2c/DUT/sda_i
add wave -noupdate /tb_vme64x_i2c/DUT/sda_o
add wave -noupdate /tb_vme64x_i2c/DUT/scl_i
add wave -noupdate /tb_vme64x_i2c/cmp_master/sda_oen
add wave -noupdate /tb_vme64x_i2c/DUT/sda_en_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {697592847 ps} 0}
WaveRestoreCursors {{Cursor 1} {2174207923 ps} 0}
configure wave -namecolwidth 261
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -52,4 +59,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {1050 us}
WaveRestoreZoom {2070580 ns} {2595580 ns}
hdl/vme64x_i2c/syn/conv_ttl_blo_v2.gise
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......@@ -106,7 +106,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363684728" xil_pn:in_ck="-3906018761073273710" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363684714">
<transform xil_pn:end_ts="1363970284" xil_pn:in_ck="-3906018761073273710" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363970272">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -128,7 +128,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363684817" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363684812">
<transform xil_pn:end_ts="1363970292" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363970284">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -137,11 +137,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363684849" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363684817">
<transform xil_pn:end_ts="1363970324" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363970292">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_v2_map.map"/>
......@@ -152,7 +150,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1363684881" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363684849">
<transform xil_pn:end_ts="1363970356" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363970324">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -167,7 +165,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363684900" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363684881">
<transform xil_pn:end_ts="1363970374" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363970356">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -178,17 +176,15 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1363684950" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363684950">
<transform xil_pn:end_ts="1363970374" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363970374">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impact.cmd"/>
<outfile xil_pn:name="_impact.log"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1363684881" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363684874">
<transform xil_pn:end_ts="1363970356" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363970347">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/vme64x_i2c/test/i2c_bit_tb.vhd deleted 100644 → 0
View file @ 1d4b172e
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 12:07:51 10/26/2011
-- Design Name: i2c slave to wb_master testbench
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
-- Project Name: CTDAH
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
library work;
USE ieee.std_logic_1164.ALL;
USE work.i2c_slave_pkg.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY i2c_bit_tb IS
END i2c_bit_tb;
ARCHITECTURE behavior OF i2c_bit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component i2c_bit
port(
rst_i : IN std_logic;
wb_clk_i : IN std_logic;
sda_i : IN std_logic;
scl_i : IN std_logic;
done_o : OUT std_logic;
start_o : OUT std_logic;
pause_o : OUT std_logic;
rcved_o : OUT std_logic
);
end component;
--Inputs
signal rst_i : std_logic := '0';
signal wb_clk_i : std_logic := '0';
signal sda_i : std_logic := '0';
signal scl_i : std_logic := '0';
--Outputs
signal start_o : std_logic;
signal pause_o : std_logic;
signal rcved_o : std_logic;
signal done_o : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant wb_clk_i_period : time := 50 ns; -- @ 20 MHz
constant scl_i_period : time := 2500 ns; -- @ 400 KHz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2c_bit
PORT MAP (rst_i => rst_i,
wb_clk_i => wb_clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => start_o,
pause_o => pause_o,
rcved_o => rcved_o,
done_o => done_o);
-- Clock process definitions
wb_clk_i_process :process
begin
wb_clk_i <= '1';
wait for wb_clk_i_period/2;
wb_clk_i <= '0';
wait for wb_clk_i_period/2;
end process;
scl_i_process :process
begin
scl_i <= '1';
wait for scl_i_period/2;
scl_i <= '0';
wait for scl_i_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure init_cond is
begin
sda_i <= '1';
scl_i <= 'Z';
end init_cond;
procedure rst is
begin
wait for wb_clk_i_period*2;
rst_i <= '1';
wait for wb_clk_i_period*2;
rst_i <= '0';
wait for wb_clk_i_period*2;
end rst;
procedure start is
begin
sda_i <= '1';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '0';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end start;
procedure addr_send(addr : STD_LOGIC_VECTOR(6 downto 0)) is
begin
for i in 0 to 6 loop
sda_i <= addr(i);
wait for scl_i_period;
end loop;
end addr_send;
procedure pause is
begin
sda_i <= '0';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '1';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end pause;
begin
init_cond;
rst;
start;
addr_send("0101100");
pause;
wait;
end process;
END;
hdl/vme64x_i2c/test/i2c_master_driver.vhd deleted 100644 → 0
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hdl/vme64x_i2c/test/i2c_slave_top_tb.vhd deleted 100644 → 0
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hdl/vme64x_i2c/test/i2c_tb_pkg.vhd deleted 100644 → 0
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hdl/vme64x_i2c/test/log/i2c_master_driver.txt deleted 100644 → 0
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pcb/doc/order-record.ods
View file @ f03f5447
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