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Conv TTL Blocking
Commit f1fe4077 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Improving testbench. Readbacks of the whole system are OK.

parent 6c5f2ce5
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hdl/IMAGES/image1/project/image1.gise
View file @ f1fe4077
......@@ -60,7 +60,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1355158578" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1355158578">
<transform xil_pn:end_ts="1355240543" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1355240543">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
......@@ -112,7 +112,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1355158578" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1355158578">
<transform xil_pn:end_ts="1355240543" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1355240543">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
......@@ -152,7 +152,7 @@
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1355158579" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1355158578">
<transform xil_pn:end_ts="1355240544" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1355240543">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="image1_top_tb.fdo"/>
......
hdl/IMAGES/image1/project/waveform/wave.do
View file @ f1fe4077
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hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ f1fe4077
This diff is collapsed.
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ f1fe4077
......@@ -124,6 +124,39 @@ package image1_top_tb_pkg is
DTX : STD_LOGIC_VECTOR(work.i2c_slave_pkg.r_DTX'a_length - 1 downto 0);
end record;
type t_MULTIBOOT_regs is
record
CTR0 : work.multiboot_pkg.r_CTR0;
CTR1 : work.multiboot_pkg.r_CTR1;
STAT : work.multiboot_pkg.r_STAT;
MBA : work.multiboot_pkg.r_BAR;
GBA : work.multiboot_pkg.r_BAR;
MBA_ICAP : STD_LOGIC_VECTOR (23 downto 0);
GBA_ICAP : STD_LOGIC_VECTOR (23 downto 0);
end record;
type t_MULTIBOOT_regs_slv is
record
CTR0 : STD_LOGIC_VECTOR (31 downto 0);
CTR1 : STD_LOGIC_VECTOR (31 downto 0);
STAT : STD_LOGIC_VECTOR (31 downto 0);
MBA : STD_LOGIC_VECTOR (31 downto 0);
GBA : STD_LOGIC_VECTOR (31 downto 0);
MBA_ICAP : STD_LOGIC_VECTOR (31 downto 0);
GBA_ICAP : STD_LOGIC_VECTOR (31 downto 0);
end record;
type t_M25P32_regs is
record
FMI : work.m25p32_pkg.r_FMI;
SR_m25p32 : work.m25p32_pkg.r_SR_m25p32;
end record;
type t_M25P32_regs_slv is
record
FMI : STD_LOGIC_VECTOR(31 downto 0);
SR_m25p32 : STD_LOGIC_VECTOR(31 downto 0);
end record;
type t_wr_fw_reg is
record
......@@ -223,14 +256,25 @@ package image1_top_tb_pkg is
:= X"0"&"001"& work.m25p32_pkg.c_DATA_READ_addr &"00";
constant c_M25P32_DATA_WRITE_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"0"&"001"& work.m25p32_pkg.c_DATA_WRITE_addr &"00";
constant c_M25P32_DATA_WRITE_base_addr : UNSIGNED(15 downto 0)
:= UNSIGNED(c_M25P32_DATA_WRITE_addr);
function f_STD_LOGIC_VECTOR(fw_regs : t_wr_fw_reg) return t_wr_fw_reg_slv;
function f_STD_LOGIC_VECTOR(multiboot_regs : t_MULTIBOOT_regs)
return t_MULTIBOOT_regs_slv;
function f_STD_LOGIC_VECTOR(m25p32_regs : t_M25P32_regs)
return t_M25P32_regs_slv;
end image1_top_tb_pkg;
package body image1_top_tb_pkg is
--! Translation function to help checking within
--! image1_top_tb
--! @brief multiboot_regs Aggregate of the register in multiboot core
function f_STD_LOGIC_VECTOR(fw_regs : t_wr_fw_reg) return t_wr_fw_reg_slv is
variable v_return : t_wr_fw_reg_slv;
begin
......@@ -247,4 +291,33 @@ package body image1_top_tb_pkg is
return v_return;
end f_STD_LOGIC_VECTOR;
--! Translation function to help checking within
--! image1_top_tb
--! @brief multiboot_regs Aggregate of the register in multiboot core
function f_STD_LOGIC_VECTOR(multiboot_regs : t_MULTIBOOT_regs)
return t_MULTIBOOT_regs_slv is
variable v_return : t_MULTIBOOT_regs_slv;
begin
v_return.CTR0 := X"000000"&f_STD_LOGIC_VECTOR(multiboot_regs.CTR0);
v_return.CTR1 := X"000000"&f_STD_LOGIC_VECTOR(multiboot_regs.CTR1);
v_return.STAT := X"0000"&f_STD_LOGIC_VECTOR(multiboot_regs.STAT);
v_return.MBA := f_STD_LOGIC_VECTOR(multiboot_regs.MBA);
v_return.GBA := f_STD_LOGIC_VECTOR(multiboot_regs.GBA);
v_return.MBA_ICAP := X"00"&multiboot_regs.MBA_ICAP;
v_return.GBA_ICAP := X"00"&multiboot_regs.GBA_ICAP;
return v_return;
end function;
--! Translation function to help checking within
--! image1_top_tb
--! @brief m25p32_regs Aggregate of the register in m25p32 core
function f_STD_LOGIC_VECTOR(m25p32_regs : t_M25P32_regs)
return t_M25P32_regs_slv is
variable v_return : t_M25P32_regs_slv;
begin
v_return.FMI := X"00"&f_STD_LOGIC_VECTOR(m25p32_regs.FMI);
v_return.SR_m25p32 := X"000000"&f_STD_LOGIC_VECTOR(m25p32_regs.SR_m25p32);
return v_return;
end function;
end image1_top_tb_pkg;
hdl/IMAGES/image1/test/log/i2c_master_driver.txt
View file @ f1fe4077
......@@ -6,17 +6,163 @@
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
3 OK READ [ADDRESS|0]
3 OK READ WISHBONE HIGH
3 OK READ WISHBONE LOW
3 OK READ [ADDRESS|0]
3 OK WRITE [ADDRESS|0]
3 OK WRITE WISHBONE HIGH
3 OK WRITE WISHBONE LOW
3 OK WRITE READ DATA 0
3 OK WRITE READ DATA 1
3 OK WRITE READ DATA 2
3 OK WRITE READ DATA 3
4 OK READ [ADDRESS|0]
4 OK READ WISHBONE HIGH
4 OK READ WISHBONE LOW
4 OK READ [ADDRESS|0]
5 OK READ [ADDRESS|0]
5 OK READ WISHBONE HIGH
5 OK READ WISHBONE LOW
5 OK READ [ADDRESS|0]
5 OK WRITE [ADDRESS|0]
5 OK WRITE WISHBONE HIGH
5 OK WRITE WISHBONE LOW
5 OK WRITE READ DATA 0
5 OK WRITE READ DATA 1
5 OK WRITE READ DATA 2
5 OK WRITE READ DATA 3
6 OK READ [ADDRESS|0]
6 OK READ WISHBONE HIGH
6 OK READ WISHBONE LOW
6 OK READ [ADDRESS|0]
7 OK WRITE [ADDRESS|0]
7 OK WRITE WISHBONE HIGH
7 OK WRITE WISHBONE LOW
7 OK WRITE READ DATA 0
7 OK WRITE READ DATA 1
7 OK WRITE READ DATA 2
7 OK WRITE READ DATA 3
8 OK READ [ADDRESS|0]
8 OK READ WISHBONE HIGH
8 OK READ WISHBONE LOW
8 OK READ [ADDRESS|0]
9 OK WRITE [ADDRESS|0]
9 OK WRITE WISHBONE HIGH
9 OK WRITE WISHBONE LOW
9 OK WRITE READ DATA 0
9 OK WRITE READ DATA 1
9 OK WRITE READ DATA 2
9 OK WRITE READ DATA 3
10 OK READ [ADDRESS|0]
10 OK READ WISHBONE HIGH
10 OK READ WISHBONE LOW
10 OK READ [ADDRESS|0]
11 OK WRITE [ADDRESS|0]
11 OK WRITE WISHBONE HIGH
11 OK WRITE WISHBONE LOW
11 OK WRITE READ DATA 0
11 OK WRITE READ DATA 1
11 OK WRITE READ DATA 2
11 OK WRITE READ DATA 3
12 OK READ [ADDRESS|0]
12 OK READ WISHBONE HIGH
12 OK READ WISHBONE LOW
12 OK READ [ADDRESS|0]
13 OK WRITE [ADDRESS|0]
13 OK WRITE WISHBONE HIGH
13 OK WRITE WISHBONE LOW
13 OK WRITE READ DATA 0
13 OK WRITE READ DATA 1
13 OK WRITE READ DATA 2
13 OK WRITE READ DATA 3
14 OK READ [ADDRESS|0]
14 OK READ WISHBONE HIGH
14 OK READ WISHBONE LOW
14 OK READ [ADDRESS|0]
15 OK WRITE [ADDRESS|0]
15 OK WRITE WISHBONE HIGH
15 OK WRITE WISHBONE LOW
15 OK WRITE READ DATA 0
15 OK WRITE READ DATA 1
15 OK WRITE READ DATA 2
15 OK WRITE READ DATA 3
16 OK READ [ADDRESS|0]
16 OK READ WISHBONE HIGH
16 OK READ WISHBONE LOW
16 OK READ [ADDRESS|0]
17 OK WRITE [ADDRESS|0]
17 OK WRITE WISHBONE HIGH
17 OK WRITE WISHBONE LOW
17 OK WRITE READ DATA 0
17 OK WRITE READ DATA 1
17 OK WRITE READ DATA 2
17 OK WRITE READ DATA 3
18 OK READ [ADDRESS|0]
18 OK READ WISHBONE HIGH
18 OK READ WISHBONE LOW
18 OK READ [ADDRESS|0]
19 OK WRITE [ADDRESS|0]
19 OK WRITE WISHBONE HIGH
19 OK WRITE WISHBONE LOW
19 OK WRITE READ DATA 0
19 OK WRITE READ DATA 1
19 OK WRITE READ DATA 2
19 OK WRITE READ DATA 3
20 OK READ [ADDRESS|0]
20 OK READ WISHBONE HIGH
20 OK READ WISHBONE LOW
20 OK READ [ADDRESS|0]
21 OK WRITE [ADDRESS|0]
21 OK WRITE WISHBONE HIGH
21 OK WRITE WISHBONE LOW
21 OK WRITE READ DATA 0
21 OK WRITE READ DATA 1
21 OK WRITE READ DATA 2
21 OK WRITE READ DATA 3
22 OK READ [ADDRESS|0]
22 OK READ WISHBONE HIGH
22 OK READ WISHBONE LOW
22 OK READ [ADDRESS|0]
23 OK WRITE [ADDRESS|0]
23 OK WRITE WISHBONE HIGH
23 OK WRITE WISHBONE LOW
23 OK WRITE READ DATA 0
23 OK WRITE READ DATA 1
23 OK WRITE READ DATA 2
23 OK WRITE READ DATA 3
24 OK READ [ADDRESS|0]
24 OK READ WISHBONE HIGH
24 OK READ WISHBONE LOW
24 OK READ [ADDRESS|0]
25 OK WRITE [ADDRESS|0]
25 OK WRITE WISHBONE HIGH
25 OK WRITE WISHBONE LOW
25 OK WRITE READ DATA 0
25 OK WRITE READ DATA 1
25 OK WRITE READ DATA 2
25 OK WRITE READ DATA 3
26 OK READ [ADDRESS|0]
26 OK READ WISHBONE HIGH
26 OK READ WISHBONE LOW
26 OK READ [ADDRESS|0]
27 OK WRITE [ADDRESS|0]
27 OK WRITE WISHBONE HIGH
27 OK WRITE WISHBONE LOW
27 OK WRITE READ DATA 0
27 OK WRITE READ DATA 1
27 OK WRITE READ DATA 2
27 OK WRITE READ DATA 3
28 OK READ [ADDRESS|0]
28 OK READ WISHBONE HIGH
28 OK READ WISHBONE LOW
28 OK READ [ADDRESS|0]
29 OK WRITE [ADDRESS|0]
29 OK WRITE WISHBONE HIGH
29 OK WRITE WISHBONE LOW
29 OK WRITE READ DATA 0
29 OK WRITE READ DATA 1
29 OK WRITE READ DATA 2
29 OK WRITE READ DATA 3
30 OK READ [ADDRESS|0]
30 OK READ WISHBONE HIGH
30 OK READ WISHBONE LOW
30 OK READ [ADDRESS|0]
31 OK WRITE [ADDRESS|0]
31 OK WRITE WISHBONE HIGH
31 OK WRITE WISHBONE LOW
31 OK WRITE READ DATA 0
31 OK WRITE READ DATA 1
31 OK WRITE
\ No newline at end of file
hdl/m25p32/rtl/m25p32_top.vhd
View file @ f1fe4077
......@@ -144,50 +144,46 @@ begin
op_finished_o <= f_OP(s_OP).OPF;
inst_m25p32_core: m25p32_core
port map (
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
port map (wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
mosi_o => prom_mosi_o,
miso_i => prom_din_i,
sclk_o => prom_cclk_o,
ss_n_o => prom_cs0_b_n_o,
mosi_o => prom_mosi_o,
miso_i => prom_din_i,
sclk_o => prom_cclk_o,
ss_n_o => prom_cs0_b_n_o,
wr_data_i => s_wr_data,
rd_data_o => s_rd_data,
SR_m25p32_i => s_SR_m25p32,
wr_data_i => s_wr_data,
rd_data_o => s_rd_data,
SR_m25p32_i => s_SR_m25p32,
rd_SPI3_o => s_rd_SPI3,
rd_SPI3_o => s_rd_SPI3,
OP_o => s_OP,
FMI_i => s_FMI
);
OP_o => s_OP,
FMI_i => s_FMI);
inst_m25p32_regs: m25p32_regs
port map (
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
rd_SPI3_i => s_rd_SPI3,
wr_data_o => s_wr_data,
rd_data_i => s_rd_data,
SR_m25p32_o => s_SR_m25p32,
OP_i => s_OP,
FMI_o => s_FMI
);
port map (wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
rd_SPI3_i => s_rd_SPI3,
wr_data_o => s_wr_data,
rd_data_i => s_rd_data,
SR_m25p32_o => s_SR_m25p32,
OP_i => s_OP,
FMI_o => s_FMI);
end Behavioral;
......
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