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C
Conv TTL Blocking
Commit f32467a1 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Added status registers at address 0x00 in memory map.

parent 2710324a
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Showing with 18 additions and 13 deletions
hdl/IMAGES/image1/project/image1.xise
View file @ f32467a1
......@@ -17,23 +17,23 @@
<files>
<file xil_pn:name="../rtl/image1_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../rtl/image1_led_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../rtl/image1_wrappers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../top/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
......@@ -41,7 +41,7 @@
</file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
......@@ -81,7 +81,7 @@
</file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
......@@ -141,7 +141,7 @@
</file>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
......@@ -188,6 +188,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../rtl/statregs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
</files>
<properties>
......@@ -409,6 +413,7 @@
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ f32467a1
......@@ -151,15 +151,15 @@ architecture Behavioral of image1_core is
constant c_addresses : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (--c_addr_m25p32,
--c_addr_multiboot,
c_addr_statregs,
c_addr_i2c_bridge);
c_addr_i2c_bridge,
c_addr_statregs);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves - 1 downto 0)
:= (--c_mask_m25p32,
-- c_mask_multiboot,
c_mask_statregs,
c_mask_i2c_bridge);
c_mask_i2c_bridge,
c_mask_statregs);
--============================================================================
-- Component declarations
......@@ -449,7 +449,7 @@ begin
(
rst_n_i => rst_n,
clk_sys_i => clk_50,
wb_adr_i => xbar_master_out(c_slave_statregs).adr,
wb_adr_i => xbar_master_out(c_slave_statregs).adr(2 downto 2),
wb_dat_i => xbar_master_out(c_slave_statregs).dat,
wb_dat_o => xbar_master_in(c_slave_statregs).dat,
wb_cyc_i => xbar_master_out(c_slave_statregs).cyc,
......
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