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Updated python scripts to use memory map for gateware v4

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software/convttl_regs.py 0 → 100644
View file @ f42db4c4
#!/usr/bin/python
#===============================================================================
# CERN (BE-CO-HT)
# Memory map for CONV-TTL-BLO
#===============================================================================
# author: Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation: 02.02.2017
#
# version: 1.0
#
# description:
# This script contains memory map for CONV-TTL-BLO, gateware v4.
#
#===============================================================================
# GNU LESSER GENERAL PUBLIC LICENSE
#===============================================================================
# This source file is free software; you can redistribute it and/or modify it
# under the terms of the GNU Lesser General Public License as published by the
# Free Software Foundation; either version 2.1 of the License, or (at your
# option) any later version. This source is distributed in the hope that it
# will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
# See the GNU Lesser General Public License for more details. You should have
# received a copy of the GNU Lesser General Public License along with this
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
#===============================================================================
# TODO: -
#===============================================================================
# Memory map for gateware v4
SR = 0x04
ERR = 0x08
CR = 0x0c
CH1TTLPCR = 0x10
CH2TTLPCR = 0x14
CH3TTLPCR = 0x18
CH4TTLPCR = 0x1c
CH5TTLPCR = 0x20
CH6TTLPCR = 0x24
CH1BLOPCR = 0x28
CH2BLOPCR = 0x2c
CH3BLOPCR = 0x30
CH4BLOPCR = 0x34
CH5BLOPCR = 0x38
CH6BLOPCR = 0x3c
TVLR = 0x40
TVHR = 0x44
TBMR = 0x48
TBCYR = 0x4c
TBTLR = 0x50
TBTHR = 0x54
TBCSR = 0x58
CH1LTSCYR = 0x5c
UIDLR = 0xac
UIDHR = 0xb0
TEMPR = 0xb4
software/diag/README.txt
View file @ f42db4c4
......@@ -6,6 +6,6 @@ clrchxpcr.py -- Clears the channel pulse counter registers
getsr.py -- Read the board's SR and print the list of fields
mantrig.py -- Manually trigger a pulse on a selected channel
rdchxpcr.py -- Read the channel pulse counter registers
setsr.py -- Set the board's SR, typically for clearing error bits
seterr.py -- Set the board's ERR, typically for clearing error bits
therm.py -- Get the unique ID and temperature from the
DS18B20 thermometer on-board the CONV-TTL-BLO
DS18B20 thermometer on-board the CONV-TTL-BLO
software/diag/clrchxpcr.py
View file @ f42db4c4
......@@ -4,10 +4,11 @@
# Clear CHxPCR registers on CONV-TTL-BLO
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation:
#
# version: 1.0
# version: 1.1
#
# description:
# This script is used to clear the input channel counters on the CONV-TTL-BLO
......@@ -27,8 +28,9 @@
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
# TODO: -
#===============================================================================
import time
import sys
......@@ -36,6 +38,8 @@ import time
sys.path.append("../ei2c")
from ei2c import *
import ei2cdefine
sys.path.append("..")
import convttl_regs as regs
if __name__ == "__main__":
......@@ -71,20 +75,14 @@ if __name__ == "__main__":
# Print which board is detected in the selected slot
bid = testelma.get_bid(slot)
# Clear channel
testelma.write(slot, 0x0c, 0)
testelma.write(slot, 0x10, 0)
testelma.write(slot, 0x14, 0)
testelma.write(slot, 0x18, 0)
testelma.write(slot, 0x1c, 0)
testelma.write(slot, 0x20, 0)
# Clear counters
for i in range(6):
testelma.write(slot, regs.CH1TTLPCR + 4 * i, 0)
testelma.write(slot, regs.CH1BLOPCR + 4 * i, 0)
# Print channel counter values, close and exit
print("CH1: %d" % testelma.read(slot, 0x0c))
print("CH2: %d" % testelma.read(slot, 0x10))
print("CH3: %d" % testelma.read(slot, 0x14))
print("CH4: %d" % testelma.read(slot, 0x18))
print("CH5: %d" % testelma.read(slot, 0x1c))
print("CH6: %d" % testelma.read(slot, 0x20))
testelma.close()
# Print channel counter values
for i in range(6):
print("CH%d\tTTL: %d" % (i + 1, testelma.read(slot, regs.CH1TTLPCR + i*4)))
print(" \tBLO: %d" % (testelma.read(slot, regs.CH1BLOPCR + i*4)))
testelma.close()
software/diag/getsr.py
View file @ f42db4c4
......@@ -4,10 +4,11 @@
# Retrieve gateware version from CONV-TTL-BLO board
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation:
#
# version: 1.0
# version: 1.1
#
# description:
# This script retrieves the value of the CONV-TTL-BLO status register and
......@@ -29,14 +30,16 @@
# last changes:
# 2014-05-02 Theodor Stana Changed to print the bits of the SR
# in turn.
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
# TODO: -
#===============================================================================
import sys
sys.path.append("../ei2c")
from ei2c import *
import ei2cdefine
sys.path.append("..")
import convttl_regs as regs
if __name__ == "__main__":
......@@ -72,7 +75,7 @@ if __name__ == "__main__":
bid = testelma.get_bid(slot)
# Get status register value and print
v = testelma.read(slot, 0x4)
v = testelma.read(slot, regs.SR)
print("Status register : 0x%08x" % v)
print("===============================")
......@@ -81,6 +84,10 @@ if __name__ == "__main__":
min = v & 0x0f
print("Gateware version : v%d.%d (0x%02x)" % (maj, min, v & 0xff))
if maj < 4:
print("This tool works with gateware v4. Please upgrade your gateware.")
sys.exit()
# Strip SWITCHES and print
switches = (v & 0xff00) >> 8
print("Switches : 0x%02x" % switches)
......@@ -92,9 +99,13 @@ if __name__ == "__main__":
(((maj == 0) and (min < 2)) or ((maj != 0) and (maj < 3)))):
switches ^= 0xff
if (switches & 0x80):
print(" TTL repetition : on")
print(" TTL mode : TTL")
else:
print(" TTL repetition : off")
print(" TTL mode : TTL-BAR")
if (switches & 0x02):
print(" Pulse length : short (250 ns)")
else:
print(" Pulse length : long (1.25 us)")
if (switches & 0x01):
print(" Glitch filter : on")
else:
......@@ -114,16 +125,13 @@ if __name__ == "__main__":
if ((maj == 0) and (min < 2)) or (maj < 3):
print("-------------------------------")
# Strip the other status bits and print
print("I2C timeout error : %s" % ("{0:#01b}".format(int(bool(v & (1 << 22))))[2]))
print("White Rabbit pres. : %s" % ("{0:#01b}".format(int(bool(v & (1 << 23))))[2]))
print("I2C address error : %s" % ("{0:#01b}".format(int(bool(v & (1 << 24))))[2]))
print("Pulse miss error : 0x%02x" % ((v & 0x7e000000) >> 24))
print(" CH1 : %s" % ("{0:#01b}".format(int(bool(v & (1 << 25))))[2]))
print(" CH2 : %s" % ("{0:#01b}".format(int(bool(v & (1 << 26))))[2]))
print(" CH3 : %s" % ("{0:#01b}".format(int(bool(v & (1 << 27))))[2]))
print(" CH4 : %s" % ("{0:#01b}".format(int(bool(v & (1 << 28))))[2]))
print(" CH5 : %s" % ("{0:#01b}".format(int(bool(v & (1 << 29))))[2]))
print(" CH6 : %s" % ("{0:#01b}".format(int(bool(v & (1 << 30))))[2]))
# Hardware version
hwver = (v & 0x03c00000) >> 22
print("Hardware version : %s"
% (str(hwver) if hwver >= 4 else "3 or below" ))
# White Rabbit present
wrpres = (v & 0x04000000) >> 8
print("White Rabbit : %s" % ("present" if wrpres else "absent"))
testelma.close()
software/diag/mantrig.py
View file @ f42db4c4
......@@ -4,10 +4,11 @@
# Manually trigger a pulse
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation:
#
# version: 1.0
# version: 1.1
#
# description:
# This script can be used to manually trigger a pulse on the CONV-TTL-BLO
......@@ -27,8 +28,9 @@
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
# TODO: -
#===============================================================================
import time
import sys
......@@ -36,6 +38,8 @@ import time
sys.path.append("../ei2c")
from ei2c import *
import ei2cdefine
sys.path.append("..")
import convttl_regs as regs
if __name__ == "__main__":
......@@ -71,14 +75,12 @@ if __name__ == "__main__":
# Print which board is detected in the selected slot
bid = testelma.get_bid(slot)
# Send magic sequence
testelma.write(slot, 0x8, 0xde << 2)
testelma.write(slot, 0x8, 0xad << 2)
testelma.write(slot, 0x8, 0xbe << 2)
testelma.write(slot, 0x8, 0xef << 2)
# Ask for which channel to trigger on, trigger, close and exit
# Ask for which channel to trigger on
chan = input("chan (1..6): ")
testelma.write(slot, 0x8, chan << 2)
testelma.close()
# Send the magic sequence & the channel number
sequence = (0xde, 0xad, 0xbe, 0xef, chan) # password and then channel
for b in sequence:
testelma.write(slot, regs.CR, (b << 2) & 0x3FC)
testelma.close()
software/diag/rdchxpcr.py
View file @ f42db4c4
......@@ -4,10 +4,11 @@
# Read CHxPCR registers on CONV-TTL-BLO
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation:
#
# version: 1.0
# version: 1.1
#
# description:
# This script is used to read the input channel counters on the CONV-TTL-BLO
......@@ -27,8 +28,9 @@
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
# TODO: -
#===============================================================================
import time
import sys
......@@ -36,6 +38,8 @@ import time
sys.path.append("../ei2c")
from ei2c import *
import ei2cdefine
sys.path.append("..")
import convttl_regs as regs
if __name__ == "__main__":
......@@ -71,12 +75,9 @@ if __name__ == "__main__":
# Print which board is detected in the selected slot
bid = testelma.get_bid(slot)
# Print channel counter values, close and exit
print("CH1: %d" % testelma.read(slot, 0x0c))
print("CH2: %d" % testelma.read(slot, 0x10))
print("CH3: %d" % testelma.read(slot, 0x14))
print("CH4: %d" % testelma.read(slot, 0x18))
print("CH5: %d" % testelma.read(slot, 0x1c))
print("CH6: %d" % testelma.read(slot, 0x20))
testelma.close()
# Print channel counter values
for i in range(6):
print("CH%d\tTTL: %d" % (i + 1, testelma.read(slot, regs.CH1TTLPCR + i*4)))
print(" \tBLO: %d" % (testelma.read(slot, regs.CH1BLOPCR + i*4)))
testelma.close()
software/diag/setsr.py → software/diag/seterr.py
View file @ f42db4c4
#!/usr/bin/python
#===============================================================================
# CERN (BE-CO-HT)
# Set converter board status register
# Set converter board error register
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation: 2014-05-02
#
# version: 1.0
# version: 1.1
#
# description:
# Set the converter board status register, typically for clearing set error
# bits.
# Set the converter board errors register, typically for clearing set error
# bits. Note that typically to clear an error, one has to set it to logical
# one.
#
# dependencies:
# ../ei2c/ei2c.py
......@@ -32,6 +34,8 @@
#===============================================================================
# last changes:
# 2014-05-02 Theodor Stana File created
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware,
# renamed from setsr.py to seterr.py
#===============================================================================
# TODO: -
#===============================================================================
......@@ -41,6 +45,8 @@ import sys
sys.path.append("../ei2c")
from ei2c import *
import ei2cdefine
sys.path.append("..")
import convttl_regs as regs
if __name__ == "__main__":
......@@ -76,15 +82,15 @@ if __name__ == "__main__":
# Print which board is detected in the selected slot
bid = testelma.get_bid(slot)
# Get status register value, set and re-print
v = testelma.read(slot, 0x4)
print("SR (pre-set) : 0x%08x" % v)
print("==========================")
v = raw_input("Value to set : 0x")
# Get error register value, set and re-print
v = testelma.read(slot, regs.ERR)
print("ERR (pre-set) : 0x%08x" % v)
print("===========================")
v = raw_input("Value to set : 0x")
v = int(v, 16)
testelma.write(slot, 0x4, v)
print("==========================")
v = testelma.read(slot, 0x4)
print("SR (post-set) : 0x%08x" % v)
testelma.write(slot, regs.ERR, v)
print("===========================")
v = testelma.read(slot, regs.ERR)
print("ERR (post-set) : 0x%08x" % v)
testelma.close()
software/diag/therm.py
View file @ f42db4c4
......@@ -4,10 +4,11 @@
# Read the CONV-TTL-BLO board ID and current temperature from DS18B20 chip
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation:
#
# version: 1.0
# version: 1.1
#
# description:
# The script implements some classes to communicate to the OpenCores One-Wire
......@@ -28,8 +29,10 @@
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2017-02-02 M. Suminski Updated to work with gateware v4
# (read regs storing UID & temperature)
#===============================================================================
# TODO: -
# TODO: -
#===============================================================================
# Import system modules
import sys
......@@ -40,183 +43,9 @@ import os
sys.path.append("../ei2c")
from ei2c import *
import ei2cdefine
sys.path.append("..")
import convttl_regs as regs
##------------------------------------------------------------------------------
## OneWire class
##------------------------------------------------------------------------------
class COpenCoresOneWire:
R_CSR = 0x0
R_CDR = 0x4
CSR_DAT_MSK = (1<<0)
CSR_RST_MSK = (1<<1)
CSR_OVD_MSK = (1<<2)
CSR_CYC_MSK = (1<<3)
CSR_PWR_MSK = (1<<4)
CSR_IRQ_MSK = (1<<6)
CSR_IEN_MSK = (1<<7)
CSR_SEL_OFS = 8
CSR_SEL_MSK = (0xF<<8)
CSR_POWER_OFS = 16
CSR_POWER_MSK = (0xFFFF<<16)
CDR_NOR_MSK = (0xFFFF<<0)
CDR_OVD_OFS = 16
CDR_OVD_MSK = (0XFFFF<<16)
def wr_reg(self, addr, val):
self.bus.write(self.cslot, self.base + addr,val)
def rd_reg(self,addr):
return self.bus.read(self.cslot, self.base + addr)
def __init__(self, bus, cslot, base, clk_div_nor, clk_div_ovd):
self.bus = bus
self.base = base
self.cslot = cslot
data = (((clk_div_nor & self.CDR_NOR_MSK) |
((clk_div_ovd<<self.CDR_OVD_OFS) & self.CDR_OVD_MSK)))
self.wr_reg(self.R_CDR, data)
def reset(self, port):
data = (((port<<self.CSR_SEL_OFS) & self.CSR_SEL_MSK) |
self.CSR_CYC_MSK |
self.CSR_RST_MSK)
self.wr_reg(self.R_CSR, data)
tmo = 100
while(self.rd_reg(self.R_CSR) & self.CSR_CYC_MSK):
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: TempID IC20: Not responding"
print(msg)
reg = self.rd_reg(self.R_CSR)
return ~reg & self.CSR_DAT_MSK
def slot(self, port, bit):
data = (((port<<self.CSR_SEL_OFS) & self.CSR_SEL_MSK) |
self.CSR_CYC_MSK |
(bit & self.CSR_DAT_MSK))
self.wr_reg(self.R_CSR, data)
tmo = 100
while(self.rd_reg(self.R_CSR) & self.CSR_CYC_MSK):
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: TempID IC20: Not responding"
print(msg)
reg = self.rd_reg(self.R_CSR)
return reg & self.CSR_DAT_MSK
def read_bit(self, port):
return self.slot(port, 0x1)
def write_bit(self, port, bit):
return self.slot(port, bit)
def read_byte(self, port):
data = 0
for i in range(8):
data |= self.read_bit(port) << i
return data
def write_byte(self, port, byte):
data = 0
byte_old = byte
for i in range(8):
data |= self.write_bit(port, (byte & 0x1)) << i
byte >>= 1
if(byte_old == data):
return 0
else:
return -1
def write_block(self, port, block):
if(160 < len(block)):
return -1
data = []
for i in range(len(block)):
data.append(self.write_byte(port, block[i]))
return data
def read_block(self, port, length):
if(160 < length):
return -1
data = []
for i in range(length):
data.append(self.read_byte(port))
return data
##------------------------------------------------------------------------------
## DS18B20 class
##------------------------------------------------------------------------------
class CDS18B20:
ROM_SEARCH = 0xF0
ROM_READ = 0x33
ROM_MATCH = 0x55
ROM_SKIP = 0xCC
ROM_ALARM_SEARCH = 0xEC
CONVERT_TEMP = 0x44
WRITE_SCRATCHPAD = 0x4E
READ_SCRATCHPAD = 0xBE
COPY_SCRATCHPAD = 0x48
RECALL_EEPROM = 0xB8
READ_POWER_SUPPLY = 0xB4
def __init__(self, onewire, port):
self.onewire = onewire
self.port = port
def read_serial_number(self):
if(1 != self.onewire.reset(self.port)):
msg = "ERROR: TempID IC20: Not responding"
print(msg)
else:
err = self.onewire.write_byte(self.port, self.ROM_READ)
if err != 0:
msg = "ERROR: TempID IC20: Write failed"
print(msg)
family_code = self.onewire.read_byte(self.port)
serial_number = 0
for i in range(6):
serial_number |= self.onewire.read_byte(self.port) << (i*8)
crc = self.onewire.read_byte(self.port)
return ((crc<<56) | (serial_number<<8) | family_code)
def access(self, serial_number):
if(1 != self.onewire.reset(self.port)):
msg = "ERROR: TempID IC20: Not responding"
print(msg)
else:
err = self.onewire.write_byte(self.port, self.ROM_MATCH)
block = []
for i in range(8):
block.append(serial_number & 0xFF)
serial_number >>= 8
self.onewire.write_block(self.port, block)
return 0
def read_temp(self, serial_number):
err = self.access(serial_number)
err = self.onewire.write_byte(self.port, self.CONVERT_TEMP)
time.sleep(0.8)
err = self.access(serial_number)
err = self.onewire.write_byte(self.port, self.READ_SCRATCHPAD)
data = self.onewire.read_block(self.port, 9)
temp = (data[1] << 8) | (data[0])
if(temp & 0x1000):
temp = -0x10000 + temp
temp = temp/16.0
return temp
##------------------------------------------------------------------------------
## main
##------------------------------------------------------------------------------
if __name__ == "__main__":
FAMILY_CODE = 0x28
......@@ -231,8 +60,8 @@ if __name__ == "__main__":
ip = raw_input("ELMA crate IP or hostname : ")
user = raw_input("ELMA crate user name : ")
pwd = raw_input("ELMA crate password : ")
elma = EI2C(ip, user, pwd)
elma.open()
testelma = EI2C(ip, user, pwd)
testelma.open()
# Ask for slot number
while 1:
......@@ -250,21 +79,12 @@ if __name__ == "__main__":
print("Unexpected error: ", sys.exc_info()[0])
# Print which board is detected in the selected slot
bid = elma.get_bid(slot)
# CONV-TTL-BLO gateware changed memory map in v3.0 and golden v0.2
gwvers = elma.read(slot, 0x04) & 0xff
baseaddr = 0x200
if (bid == "TBLO"):
if ((gwvers >= 0x10) and (gwvers <= 0x22)):
baseaddr = 0x080
# Create onewire and thermometer objects
onewire = COpenCoresOneWire(elma, slot, baseaddr, 99, 19)
ds18b20 = CDS18B20(onewire, 0)
bid = testelma.get_bid(slot)
# Reading of unique ID
unique_id = ds18b20.read_serial_number()
unique_id = ((testelma.read(slot, regs.UIDHR) << 32)
| testelma.read(slot, regs.UIDLR))
if(unique_id == -1):
msg = "ERROR: TempID IC20: Unable to read 1-wire thermometer"
print(msg)
......@@ -272,12 +92,12 @@ if __name__ == "__main__":
print("Unique ID: %.12X" % (unique_id))
# Reading of temperature
temp = ds18b20.read_temp(unique_id)
print("Current temperature: %3.3f" % temp)
temp = testelma.read(slot, regs.TEMPR) / 16.0
print("Current temperature: %3.3f *C" % temp)
# Cheking if received values are reasonable
if temp < 10.0 or temp > 50.0:
msg = "ERROR: TempID IC20: Temperature: %d out of range[10 .. 50oC]" % (temp)
msg = "ERROR: TempID IC20: Temperature: %d out of range[10 .. 50*C]" % (temp)
print(msg)
if((unique_id & 0xFF) != FAMILY_CODE):
......@@ -285,5 +105,4 @@ if __name__ == "__main__":
msg = "ERROR: TempID IC20: Invalid family code: 0x%.8X" % (family_code)
print(msg)
elma.close()
testelma.close()
software/diag/timetag/README.txt
View file @ f42db4c4
......@@ -37,11 +37,11 @@ following:
(<USEDW>) <channel mask> : <TAI value>.<seconds value>
where
<USEDW> -- the TFCSR.USED field
<channel mask> -- the TFMR.CHAN field
<USEDW> -- the TBCSR.USED field
<channel mask> -- the TBMR.CHAN field
<TAI value> -- TAI value obtained by concatenating the bit fields of the
TFTLR and TFTHR registers
<seconds value> -- TFCYR * 8
TBTLR and TBTHR registers
<seconds value> -- TBCYR * 8
tsdiff.py
---------
......
software/diag/timetag/getlatestts.py
View file @ f42db4c4
......@@ -7,7 +7,7 @@
#
# date of creation: 2014-08-18
#
# version: 1.0
# version: 1.1
#
# description:
#
......@@ -29,6 +29,7 @@
#===============================================================================
# last changes:
# 2014-08-18 Theodor Stana File created
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
#===============================================================================
......@@ -36,6 +37,8 @@ import sys
sys.path.append("../../ei2c")
from ei2c import *
import ei2cdefine
sys.path.append("../..")
import convttl_regs as regs
if __name__ == "__main__":
......@@ -71,15 +74,14 @@ if __name__ == "__main__":
bid = testelma.get_bid(slot)
# Get and print latest timestamps
addr = 0x40
addr = regs.CH1LTSCYR
for i in range(6):
cyc = testelma.read(slot, addr)
tail = testelma.read(slot, addr + 4)
taih = testelma.read(slot, addr + 8) & 0x000000ff
cyc = testelma.read(slot, addr) # LTSCYR
tail = testelma.read(slot, addr + 4) # LTSTLR
taih = testelma.read(slot, addr + 8) & 0x000000ff # LTSTHR
ns = cyc * 8
s = (taih << 32) | tail
print("CH%d: %d.%09d sec" % (i+1, s, ns))
addr += 0x0c
testelma.close()
software/diag/timetag/rdtb.py
View file @ f42db4c4
......@@ -4,10 +4,11 @@
# Read the CONV-TTL-BLO timetag buffer
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation:
#
# version: 1.0
# version: 1.1
#
# description:
# This script demonstrates reading the CONV-TTL-BLO timetag buffer down to the
......@@ -27,14 +28,17 @@
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
# TODO: -
#===============================================================================
import sys
sys.path.append("../../ei2c")
from ei2c import *
import ei2cdefine
import math
sys.path.append("../..")
import convttl_regs as regs
if __name__ == "__main__":
......@@ -86,7 +90,7 @@ if __name__ == "__main__":
print("Error: " + sys.exc_info()[0]);
# Read while FIFO is not empty
csr = testelma.read(slot, 0x3c)
csr = testelma.read(slot, regs.TBCSR)
empty = csr & (1 << 17)
used = csr & 0x7f
......@@ -94,9 +98,9 @@ if __name__ == "__main__":
while not empty:
# Read cycles and seconds counters
cyc = testelma.read(slot, 0x30)
sl = testelma.read(slot, 0x34)
sh = testelma.read(slot, 0x38)
cyc = testelma.read(slot, regs.TBCYR)
sl = testelma.read(slot, regs.TBTLR)
sh = testelma.read(slot, regs.TBTHR)
# The seconds counter indicates actual seconds; the cycles counter
# indicates 8-ns cycles, so convert to ns
......@@ -104,14 +108,14 @@ if __name__ == "__main__":
ns = cyc*8
# Get contents of TBCSR
csr = testelma.read(slot, 0x3c)
csr = testelma.read(slot, regs.TBCSR)
empty = csr & (1 << 17)
if (empty):
break
used = csr & 0x7f
# Get channel mask from meta register
ch = testelma.read(slot, 0x2c) & 0x3f
ch = testelma.read(slot, regs.TBMR) & 0x3f
# Increment channel counters if channel bit is set in FIFO
i = 0
......
software/diag/timetag/tsget.py
View file @ f42db4c4
......@@ -4,10 +4,11 @@
# Get the current timestamp counter value
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation:
#
# version: 1.0
# version: 1.1
#
# description:
# This script reads the TVLR and TVHR registers and prints their value to stdout.
......@@ -26,14 +27,17 @@
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
# TODO: -
#===============================================================================
import sys
sys.path.append("../../ei2c")
import time
from ei2c import *
import ei2cdefine
sys.path.append("../..")
import convttl_regs as regs
if __name__ == "__main__":
......@@ -68,8 +72,8 @@ if __name__ == "__main__":
# Print which board is detected in the selected slot
bid = testelma.get_bid(slot)
tail = testelma.read(slot, 0x24)
taih = testelma.read(slot, 0x28)
tail = testelma.read(slot, regs.TVLR)
taih = testelma.read(slot, regs.TVHR)
print("TAI counter value: %d" % ((taih << 32) | tail))
......
software/diag/timetag/tsset.py
View file @ f42db4c4
......@@ -4,10 +4,11 @@
# Set the timestamp counter value
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation:
#
# version: 1.0
# version: 1.1
#
# description:
# This script writes the TVLR and TVHR registers to set the new internal
......@@ -27,14 +28,17 @@
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
# TODO: -
#===============================================================================
import sys
sys.path.append("../../ei2c")
import time
from ei2c import *
import ei2cdefine
sys.path.append("../..")
import convttl_regs as regs
if __name__ == "__main__":
......@@ -72,14 +76,12 @@ if __name__ == "__main__":
# Set time stamp, close and exit
s = int(raw_input("Number of seconds: "))
testelma.write(slot, 0x24, s & 0xffffffff)
if s > 2**32-1:
testelma.write(slot, 0x28, s >> 32)
testelma.write(slot, regs.TVLR, s & 0xffffffff)
testelma.write(slot, regs.TVHR, s >> 32)
tail = testelma.read(slot, 0x24)
taih = testelma.read(slot, 0x28)
tail = testelma.read(slot, regs.TVLR)
taih = testelma.read(slot, regs.TVHR)
print("TAI counter value: %d" % ((taih << 32) | tail))
testelma.close()
software/regupdate/README
View file @ f42db4c4
This script connects to a create and checks that the values of the CHxPCR and
This script connects to a crate and checks that the values of the CHxPCR and
CHxLTS*R registers are not written with wrong values.
Basically, its purpose is to check that no 'sync' errors occur when the
......
software/regupdate/regupdate.py 100644 → 100755
View file @ f42db4c4
......@@ -4,6 +4,7 @@
# Long-term register update test
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation: 2014-08-25
#
......@@ -29,8 +30,10 @@
#===============================================================================
# last changes:
# 2014-08-25 Theodor Stana File created
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
# TODO: - It was not tested with gateware v4, there are now separate counters
# for TTL and blocking pulses. Blocking pulse counters are not handled.
#===============================================================================
import sys
......@@ -38,6 +41,8 @@ sys.path.append("../ei2c");
from ei2c import *
import ei2cdefine
import time
sys.path.append("..");
import convttl_regs as regs
if __name__ == "__main__":
......@@ -138,18 +143,19 @@ if __name__ == "__main__":
chltstlr_p[3] = []
chltsthr_p[3] = []
for i in range(0, 6):
chpcr[1].append(elma.read(slot, 0x0c + 4*i))
chltscyr[1].append(elma.read(slot, 0x40 + 0xc*i))
chltstlr[1].append(elma.read(slot, 0x44 + 0xc*i))
chltsthr[1].append(elma.read(slot, 0x48 + 0xc*i) & 0xff)
chpcr[1].append(elma.read(slot, regs.CH1TTLPCR + 4*i))
chltscyr[1].append(elma.read(slot, regs.CH1LTSCYR + 0xc*i))
chltstlr[1].append(elma.read(slot, regs.CH1LTSTLR + 0xc*i))
chltsthr[1].append(elma.read(slot, regs.CH1LTSTHR + 0xc*i) & 0xff)
chpcr_p[1].append(chpcr[1][i])
chltscyr_p[1].append(chltscyr[1][i])
chltstlr_p[1].append(chltstlr[1][i])
chltsthr_p[1].append(chltsthr[1][i])
chpcr[3].append(elma.read(slot+2, 0x0c + 4*i))
chltscyr[3].append(elma.read(slot+2, 0x40 + 0xc*i))
chltstlr[3].append(elma.read(slot+2, 0x44 + 0xc*i))
chltsthr[3].append(elma.read(slot+2, 0x48 + 0xc*i) & 0xff)
chpcr[3].append(elma.read(slot+2, regs.CH1TTLPCR + 4*i))
chltscyr[3].append(elma.read(slot+2, regs.CH1LTSCYR+ 0xc*i))
chltstlr[3].append(elma.read(slot+2, regs.CH1LTSTLR + 0xc*i))
chltsthr[3].append(elma.read(slot+2, regs.CH1LTSTHR + 0xc*i) & 0xff)
chpcr_p[3].append(chpcr[1][i])
chltscyr_p[3].append(chltscyr[3][i])
chltstlr_p[3].append(chltstlr[3][i])
......@@ -172,18 +178,18 @@ if __name__ == "__main__":
for i in range(0, 6):
# Read values
chpcr[slot][i] = elma.read(slot, 0x0c + 4*i)
chltscyr[slot][i] = elma.read(slot, 0x40 + 0xc*i)
chltstlr[slot][i] = elma.read(slot, 0x44 + 0xc*i)
chltsthr[slot][i] = elma.read(slot, 0x48 + 0xc*i) & 0xff
chpcr[slot][i] = elma.read(slot, regs.CH1TTLPCR + 4*i)
chltscyr[slot][i] = elma.read(slot, regs.CH1LTSCYR + 0xc*i)
chltstlr[slot][i] = elma.read(slot, regs.CH1LTSTLR + 0xc*i)
chltsthr[slot][i] = elma.read(slot, regs.CH1LTSTHR + 0xc*i) & 0xff
# check CHxPCR not lower and within a tolerance limit of value before
# check CHxTTLPCR not lower and within a tolerance limit of value before
if (chpcr[slot][i] < chpcr_p[slot][i]) or (chpcr[slot][i] > chpcr_p[slot][i] + 14000):
print("ERROR (%d / %s): CH%dPCR unexpected value (%d / %d)" % (
print("ERROR (%d / %s): CH%dTTLPCR unexpected value (%d / %d)" % (
slot, time.strftime("%Y-%m-%d-%Hh%Mm%Ss", time.localtime()),
i+1, chpcr_p[slot][i], chpcr[slot][i]))
elif (chpcr[slot][i] > chpcr_p[slot][i]+4200):
print("WARNING (%d / %s): CH%dPCR value: (%d / %d)" % (
print("WARNING (%d / %s): CH%dTTLPCR value: (%d / %d)" % (
slot, time.strftime("%Y-%m-%d-%Hh%Mm%Ss", time.localtime()),
i+1, chpcr_p[slot][i], chpcr[slot][i]))
......@@ -212,7 +218,7 @@ if __name__ == "__main__":
chltsthr_p[slot][i] = chltsthr[slot][i]
# print(slot)
# print("CH%dPCR=%d" % (i+1, chpcr[slot][i]) )
# print("CH%dTTLPCR=%d" % (i+1, chpcr[slot][i]) )
# print("CH%dPLTSCYR=%d" % (i+1, chltscyr[slot][i]) )
# print("CH%dPLTSTLR=%d" % (i+1, chltstlr[slot][i]) )
# print("CH%dPLTSTHR=%d" % (i+1, chltsthr[slot][i]) )
......@@ -222,18 +228,18 @@ if __name__ == "__main__":
for i in range(0, 6):
# Read values
chpcr[slot][i] = elma.read(slot, 0x0c + 4*i)
chltscyr[slot][i] = elma.read(slot, 0x40 + 0xc*i)
chltstlr[slot][i] = elma.read(slot, 0x44 + 0xc*i)
chltsthr[slot][i] = elma.read(slot, 0x48 + 0xc*i) & 0xff
chpcr[slot][i] = elma.read(slot, regs.CH1TTLTTLPCR + 4*i)
chltscyr[slot][i] = elma.read(slot, regs.CH1LTSCYR + 0xc*i)
chltstlr[slot][i] = elma.read(slot, regs.CH1LTSTLR + 0xc*i)
chltsthr[slot][i] = elma.read(slot, regs.CH1LTSTHR + 0xc*i) & 0xff
# check CHxPCR not lower and within a tolerance limit of value before
# check CHxTTLPCR not lower and within a tolerance limit of value before
if (chpcr[slot][i] < chpcr_p[slot][i]) or (chpcr[slot][i] > chpcr_p[slot][i] + 14000):
print("ERROR (%d / %s): CH%dPCR unexpected value (%d / %d)" % (
print("ERROR (%d / %s): CH%dTTLPCR unexpected value (%d / %d)" % (
slot, time.strftime("%Y-%m-%d-%Hh%Mm%Ss", time.localtime()),
i+1, chpcr_p[slot][i], chpcr[slot][i]))
elif (chpcr[slot][i] > chpcr_p[slot][i]+4200):
print("WARNING (%d / %s): CH%dPCR value: (%d / %d)" % (
print("WARNING (%d / %s): CH%dTTLPCR value: (%d / %d)" % (
slot, time.strftime("%Y-%m-%d-%Hh%Mm%Ss", time.localtime()),
i+1, chpcr_p[slot][i], chpcr[slot][i]))
......@@ -263,7 +269,7 @@ if __name__ == "__main__":
chltsthr_p[slot][i] = chltsthr[slot][i]
# print(slot)
# print("CH%dPCR=%d" % (i+1, chpcr[slot][i]) )
# print("CH%dTTLPCR=%d" % (i+1, chpcr[slot][i]) )
# print("CH%dPLTSCYR=%d" % (i+1, chltscyr[slot][i]) )
# print("CH%dPLTSTLR=%d" % (i+1, chltstlr[slot][i]) )
# print("CH%dPLTSTHR=%d" % (i+1, chltsthr[slot][i]) )
......
software/startuptest/startuptest.py
View file @ f42db4c4
......@@ -4,6 +4,7 @@
# Long-term "no pulses at startup" test script
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
# Maciej Suminski (maciej.suminski@cern.ch)
#
# date of creation: 2014-05-09
#
......@@ -42,8 +43,10 @@
#===============================================================================
# last changes:
# 2014-05-09 Theodor Stana File created
# 2017-02-02 M. Suminski Updated mem map to match v4 gateware
#===============================================================================
# TODO: -
# TODO: - It was not tested with gateware v4, there are now separate counters
# for TTL and blocking pulses. Blocking pulse counters are not handled.
#===============================================================================
import time
......@@ -52,6 +55,8 @@ sys.path.append("../ei2c")
from ei2c import *
import subprocess
import os
sys.path.append("..")
import convttl_regs as regs
#===============================================================================
# Change IPs/hostnames and logon credentials as appropriate
......@@ -153,13 +158,13 @@ if __name__ == "__main__":
switch.append("OFF")
f.write("TTL switch readout\n")
if not (dutelma.read(1, 0x04) & (0x8000)):
if not (dutelma.read(1, regs.SR) & (0x8000)):
switch[0] = "ON"
if not (dutelma.read(2, 0x04) & (0x8000)):
if not (dutelma.read(2, regs.SR) & (0x8000)):
switch[1] = "ON"
if not (chkelma.read(1, 0x04) & (0x8000)):
if not (chkelma.read(1, regs.SR) & (0x8000)):
switch[2] = "ON"
if not (chkelma.read(2, 0x04) & (0x8000)):
if not (chkelma.read(2, regs.SR) & (0x8000)):
switch[3] = "ON"
f.write(" DUT1: TTL switch %s\n" % switch[0])
......@@ -200,12 +205,8 @@ if __name__ == "__main__":
dut_elma_on()
# Read counters and print errors
chcnt1[0] = chkelma.read(1, 0x0c)
chcnt1[1] = chkelma.read(1, 0x10)
chcnt1[2] = chkelma.read(1, 0x14)
chcnt1[3] = chkelma.read(1, 0x18)
chcnt1[4] = chkelma.read(1, 0x1c)
chcnt1[5] = chkelma.read(1, 0x20)
for ch in range(6):
chcnt1[ch] = chkelma.read(1, regs.CH1TTLPCR + i*4)
if not (chcnt1 == cntcmp):
errcnt1 += 1
......@@ -216,12 +217,8 @@ if __name__ == "__main__":
f.write(errmsg + "\n")
#print(errmsg)
chcnt2[0] = chkelma.read(2, 0x0c)
chcnt2[1] = chkelma.read(2, 0x10)
chcnt2[2] = chkelma.read(2, 0x14)
chcnt2[3] = chkelma.read(2, 0x18)
chcnt2[4] = chkelma.read(2, 0x1c)
chcnt2[5] = chkelma.read(2, 0x20)
for ch in range(6):
chcnt2[ch] = chkelma.read(2, regs.CH1TTLPCR + i*4)
if not (chcnt2 == cntcmp):
errcnt2 += 1
......@@ -233,19 +230,9 @@ if __name__ == "__main__":
#print(errmsg)
# Clear counters
chkelma.write(1, 0x0c, 0)
chkelma.write(1, 0x10, 0)
chkelma.write(1, 0x14, 0)
chkelma.write(1, 0x18, 0)
chkelma.write(1, 0x1c, 0)
chkelma.write(1, 0x20, 0)
chkelma.write(2, 0x0c, 0)
chkelma.write(2, 0x10, 0)
chkelma.write(2, 0x14, 0)
chkelma.write(2, 0x18, 0)
chkelma.write(2, 0x1c, 0)
chkelma.write(2, 0x20, 0)
for ch in range(6):
chkelma.write(1, regs.CH1TTLPCR + i*4, 0)
chkelma.write(2, regs.CH1TTLPCR + i*4, 0)
f.write("------------------------------------------------------------\n")
......
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