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Conv TTL Blocking
Commit f53af149 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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led test fw sequence restarts on change of led test

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doc/pts/fig/memmapping.svg
View file @ f53af149
......@@ -10,7 +10,7 @@
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="460.47073"
height="122.49537"
height="115.40875"
id="svg2"
version="1.1"
inkscape:version="0.48.3.1 r9886"
......@@ -53,9 +53,9 @@
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="1.979899"
inkscape:cx="272.0516"
inkscape:cy="88.622389"
inkscape:zoom="2.8"
inkscape:cx="237.95066"
inkscape:cy="-8.4500811"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
......@@ -80,7 +80,7 @@
units="mm"
spacingx="0.5mm"
spacingy="0.5mm"
originx="-46.186035mm"
originx="-46.186034mm"
originy="-244.85889mm" />
</sodipodi:namedview>
<metadata
......@@ -98,19 +98,19 @@
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-163.65131,-62.256577)">
transform="translate(-163.65131,-69.343193)">
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="227.69249"
x="235.0731"
y="109.8425"
id="text2989"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan2991"
x="227.69249"
x="235.0731"
y="109.8425"
style="font-size:9px;font-weight:bold">vme64x_i2c</tspan></text>
style="font-size:9px;font-weight:bold">elma_i2c</tspan></text>
<g
id="g3800">
<rect
......@@ -385,12 +385,12 @@
<text
sodipodi:linespacing="125%"
id="text5318"
y="69.094467"
y="76.181084"
x="398.62204"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:9px;font-weight:bold"
y="69.094467"
y="76.181084"
x="398.62204"
id="tspan5320"
sodipodi:role="line">xwb_crossbar</tspan></text>
......
doc/pts/pts_hdlguide.pdf
View file @ f53af149
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doc/pts/pts_hdlguide.tex
View file @ f53af149
......@@ -75,9 +75,9 @@ SysMon & (ELMA) System Monitor \\
\section{Introduction}
\label{sec:intro}
This document presents a high-level view of the firmware implemented on the FPGA for the
Production Test Suite (PTS) project for the Conv-TTL-Blo board. More involved details can
Production Test Suite (PTS) project for the CONV-TTL-BLO board. More involved details can
be found by consulting the PTS HDL, which can be obtained by cloning the OHWR git repository
for the Conv-TTL-Blo PTS project \textcolor{red}{REFERENCE}.
for the CONV-TTL-BLO PTS project \textcolor{red}{REFERENCE}.
\textcolor{red}{REFERENCE THE OTHER DOCUMENTS}
......@@ -109,9 +109,9 @@ I$^2$C transfers to the CONV-TTL-BLO. More information about this can be found i
\label{sec:memmap}
Each board peripheral is accessible via a memory-mapped Wishbone interface. A
\textit{vme64x\_i2c} component \textcolor{red}{(reference)} is used alongside a Wishbone
crossbar component \textcolor{red}{(reference)} to translate the I$2$C transfers into Wishbone
transfers. Fig.~\ref{fig:memmapping} shows how these two components are connected to various
\textit{elma\_i2c} component \textcolor{red}{(reference)} is used alongside a Wishbone
crossbar component \textcolor{red}{(reference)} to translate the I$^2$C transfers into Wishbone
transfers. Figure~\ref{fig:memmapping} shows how these two components are connected to various
other memory-mapped Wishbone slaves.
\begin{figure}[h]
......@@ -120,7 +120,7 @@ other memory-mapped Wishbone slaves.
\label{fig:memmapping}
\end{figure}
The PTS firmware accesses all peripheral devices on the Conv-TTL-Blo board and sends
The PTS software accesses all peripheral devices on the CONV-TTL-BLO board and sends
device-specific commands to test their functionality. Table~\ref{tbl:memmap} shows a simplified
version of the memory map, with the base addresses of each peripheral. Details
about the memory map of each device can be found by reading the description of the
......@@ -185,7 +185,7 @@ board ID register at offset 0x4 (see Table~\ref{tbl:pts_regs}). Both registers a
\end{table}
The board ID register contains 32 read-and-writable bits which can be
used to identify the board as the Conv-TTL-Blo. It is by default set to
used to identify the board as the CONV-TTL-BLO. It is by default set to
read as the ASCII string \textbf{BLO2}, the hex value 0x424C4F32.
\begin{figure}[h]
......@@ -194,14 +194,14 @@ read as the ASCII string \textbf{BLO2}, the hex value 0x424C4F32.
\label{fig:pts-csr}
\end{figure}
Fig.~\ref{fig:pts-csr} shows the control and status register of PTS.
Figure~\ref{fig:pts-csr} shows the control and status register of PTS.
It consists of 16 bits of control data and 16 bits of status data. The first
four bits are used to enable various test functionality. The reset bit can be
used to reset all of the logic inside the FPGA when set (logic high). Caution
should therefore be taken when writing the CSR, as an erroneous write might
result in the whole logic resetting itself. When the logic is reset via a write
to this bit, the \textit{writereg} telnet command will return a \textit{Not acknowledged!},
as the reset bit also resets the \textit{vme64x\_i2c} module.
as the reset bit also resets the \textit{elma\_i2c} module.
\begin{table}[h]
\caption{CSR fields}
......@@ -251,7 +251,7 @@ are described in the module's documentation \cite{onewire}.
\section{SPI Master}
\label{sec:spi}
The two Analog Devices DACs (IC17, IC18) on the Conv-TTL-Blo board can be controlled via
The two Analog Devices DACs (IC17, IC18) on the CONV-TTL-BLO board can be controlled via
a 3-wire SPI interface. The OpenCores SPI master module is used to implement this
interface. More information can be found in the SPI master core's documentation \cite{spi}.
......@@ -312,7 +312,7 @@ module and the access registers can be found via its online documentation \cite{
\label{sec:pulse-cnt}
This module is used to count the number of sent and received pulses. It is useful in
the context of the TTL and blocking pulse repetition test. On the Conv-TTL-Blo board,
the context of the TTL and blocking pulse repetition test. On the CONV-TTL-BLO board,
there are six TTL channels, four INV-TTL channels and six blocking channels, which are
seen as sixteen pulse channels in the pulse counter module.
......@@ -389,7 +389,7 @@ The folder structure used within the PTS firmware is presented below
\begin{itemize}
\item ip\_cores/
\item Conv-TTL-Blo/hdl/
\item conv-ttl-blo/hdl/
\begin{itemize}
\item bicolor\_led\_ctrl/
\begin{itemize}
......@@ -441,12 +441,12 @@ The folder structure used within the PTS firmware is presented below
\item \textit{reset\_gen.vhd}
\end{itemize}
\end{itemize}
\item vme64x\_i2c/
\item elma\_i2c/
\begin{itemize}
\item rtl/
\begin{itemize}
\item \textit{i2c\_slave.vhd}
\item \textit{vme64x\_i2c.vhd}
\item \textit{elma\_i2c.vhd}
\end{itemize}
\end{itemize}
\end{itemize}
......@@ -454,9 +454,9 @@ The folder structure used within the PTS firmware is presented below
The ip\_cores folder contains repository files that the firmware uses, such
as the OpenCores SPI (see \ref{sec:spi})and one-wire masters (see \ref{sec:onewire}).
The modules that have been developed as part of the Conv-TTL-Blo project and can be
The modules that have been developed as part of the CONV-TTL-BLO project and can be
used in both PTS and other firmware are present in their own folders as sub-nodes of the
\textit{conv-ttl-blo/hdl/} folder. In general, the module files are present under an \textit{rtl/}
\textit{CONV-TTL-BLO/hdl/} folder. In general, the module files are present under an \textit{rtl/}
sub-folder. The \textit{pts/} folder is the main folder in the case of the PTS suite, as can
be seen from the fact that it is bolded in the folder structure above. It contains
top-level files in the \textit{top/} folder (HDL and UCF file for pin definitions) and
......@@ -475,7 +475,7 @@ the release version of the firmware.
\label{sec:get-around}
All of the PTS-specific firmware can be found in the \textit{conv-ttl-blo/hdl/pts/}
folder. The top-level file, \textit{conv-ttl-blo.vhd}, is the main-part of the firmware
folder. The top-level file, \textit{conv_ttl_blo_v2.vhd}, is the main-part of the firmware
and thus shall be the topic of this short section, where its structure and guidelines
for making changes are given. Most of the top-level ports of the file have been named
according to the schematic file netlist names. The exceptions from this are due to
......@@ -494,7 +494,7 @@ as appropriate. Ports and signals usually follow the coding guidelines at
The top module architecture is divided into sections, delimited by visible
comments. For example, code pertaining to a certain test, code pertaining
to more than one test, or general top-level code can go into a code section.
The declarative part of the architecture is organized as shown in Fig.~\ref{fig:declarative}.
The declarative part of the architecture is organized as shown in Figure~\ref{fig:declarative}.
Types are declared right after the architecture declaration, followed by con-
stant declarations, followed by component declarations, after which the var-
ious signals are declared.
......@@ -505,9 +505,9 @@ ious signals are declared.
\label{fig:body}
\end{figure}
The body of the architecture is organised as showin in Fig.~\ref{fig:body}. It begins
The body of the architecture is organised as showin in Figure~\ref{fig:body}. It begins
by instantiating a differential buffer for the 125~MHz system clock and instantiating the
\textit{reset\_gen} component. Then, the \textit{vme64x\_i2c} bridge module is instantiated
\textit{reset\_gen} component. Then, the \textit{elma\_i2c} bridge module is instantiated
along with the Wishbone crossbar that offers access to the rest of the Wishbone modules in
the design. Next, the general-purpose PTS register (see Sec.~\ref{sec:pts_regs}) module is
instantiated, followed by logic necessary for each of the tests comprising PTS.
......
hdl/pts/syn/conv_ttl_blo_v2.gise
View file @ f53af149
......@@ -72,35 +72,34 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1369821120">
<transform xil_pn:end_ts="1372354118" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1372354118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1369821120">
<transform xil_pn:end_ts="1372354118" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1372354118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1369821120">
<transform xil_pn:end_ts="1372354118" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1372354118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1369821120">
<transform xil_pn:end_ts="1372354118" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1372354118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1369821120">
<transform xil_pn:end_ts="1372354118" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1372354118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1369821120">
<transform xil_pn:end_ts="1372354118" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1372354118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1369821120" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1369821120">
<transform xil_pn:end_ts="1372354118" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1372354118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1369821184" xil_pn:in_ck="8612814983564804210" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1369821120">
<transform xil_pn:end_ts="1372354186" xil_pn:in_ck="8612814983564804210" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1372354118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +117,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1369821184" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1369821184">
<transform xil_pn:end_ts="1372354186" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1372354186">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1369821198" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1369821184">
<transform xil_pn:end_ts="1372354201" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1372354186">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +130,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1369821449" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1369821198">
<transform xil_pn:end_ts="1372354415" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1372354201">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -145,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1369821553" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1369821449">
<transform xil_pn:end_ts="1372354501" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1372354415">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -159,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1369821592" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1369821553">
<transform xil_pn:end_ts="1372354541" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1372354501">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -171,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1369821553" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1369821536">
<transform xil_pn:end_ts="1372354501" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1372354484">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @ f53af149
......@@ -617,9 +617,12 @@ architecture behav of conv_ttl_blo_v2 is
signal led_seq : unsigned(4 downto 0);
signal pulse_led_en : std_logic;
signal stat_led_en : std_logic;
signal pulse_led_en_d0 : std_logic;
signal stat_led_en_d0 : std_logic;
signal pulse_led_en_risedge: std_logic;
signal stat_led_en_risedge : std_logic;
-- PTS register signals
signal pts_state : t_pts_state;
signal cnt_halfsec : unsigned(25 downto 0);
signal rst_fr_reg : std_logic;
......@@ -1550,11 +1553,46 @@ begin
-- * test bicolor LEDs and its driving circuit (IC1)
-- * test front panel LED logic and driving circuit (IC5)
--============================================================================
-- Rising edge detector for pulse LED enable signal
p_pulse_led_en_risedge : process (clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
pulse_led_en_d0 <= '0';
pulse_led_en_risedge <= '0';
else
pulse_led_en_d0 <= pulse_led_en;
pulse_led_en_risedge <= '0';
if (pulse_led_en_d0 = '0') and (pulse_led_en = '1') then
pulse_led_en_risedge <= '1';
end if;
end if;
end if;
end process p_pulse_led_en_risedge;
-- Rising edge detector for status LED enable signal
p_stat_led_en_risedge : process (clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
stat_led_en_d0 <= '0';
stat_led_en_risedge <= '0';
else
stat_led_en_d0 <= stat_led_en;
stat_led_en_risedge <= '0';
if (stat_led_en_d0 = '0') and (stat_led_en = '1') then
stat_led_en_risedge <= '1';
end if;
end if;
end if;
end process p_stat_led_en_risedge;
-- Process to control the LED sequence counter
p_led_seq : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
if (rst_n = '0') or (stat_led_en_risedge = '1')
or (pulse_led_en_risedge = '1') then
cnt_halfsec <= (others => '0');
led_seq <= (others => '0');
elsif (pulse_led_en = '1') or (stat_led_en = '1') then
......
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