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Conv TTL Blocking
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Transfer Knowledge document updated

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%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{color}
\usepackage[table]{xcolor}
\usepackage{tabularx}
%%\usepackage{draftwatermark}
......@@ -16,7 +14,7 @@
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{
\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{January 10, 2012}
\date{January 18, 2012}
\hypersetup{
colorlinks = true,
urlcolor = blue
......@@ -64,6 +62,8 @@
\hline
0.1 & Preliminary version & January 10, 2012\\
\hline
1.0 & Final version & January 18, 2012\\
\hline
\end{tabularx}
\end{center}
......@@ -178,6 +178,7 @@
offer an easy-to-plug interface to operators.
\end{itemize}
\pagebreak
\section{Blocking boards replacement: CONV-TTL-BLO}
\subsection{Legacy boards}
......@@ -253,6 +254,125 @@
interface.
\end{itemize}
\subsubsection{V1 schematics overview}
CONV-TTL-BLO, namely CERN
\href{https://edms.cern.ch/nav/EDA-02446}{EDMS-02446 project}, is
described below.
\begin{itemize}
\item \textbf{TOP page}\\
The top page shows the main blocks in which the project is divided
into.\\
Conceptually, the left part of the schematic corresponds to the front
panel and some clocking resources, used in White Rabbit.\\
In the center we can found the FPGA, a Spartan 6 LX45T, which is the
logic core of the design. This model of Spartan is used is many
others within OWHR and BE-CO-HT, making portability of IP cores
seamless. Due to the fact of being a 6 series, SerDes functionality
will be later on used in V2 to improve sampling jitter of repeated
pulses.\\
All the blocks corresponding to the connections with VME64x
backplane and rear transistion module are over the right part of the
top schematic page.\\
\item \textbf{Power supplies}\\
Power supplies are covered in the next two pages.\\
In the first one, the rails for all the logic ICs and FPGA power is
provided. Decoupling capacitors for the FPGA are found in it. Values
and sizes of the FPGA decoupling network are consistent with the
recommendations of the vendor. All the I/O banks in the FPGA are tied
to 3.3 volts.\\
The second page corresponds the power supply needed for the
generation of the 24 volts amplitude blocking pulses. Correct
dimensioning for impulsive responses, gain and margin budgets were
calculated and verified with Texas Instruments Switcher Pro. It
should be noted here that the Power MOSFET in V1 was changed by a
similar performance one, due to soon obsolescency of the part.\\
Just as a reminder for new designers, the selection of critical
capacitors was taken with the view of a long-lasting worklife of the
boards. Hence, the use of conductive polymer capacitors is
recommended. In this design, OS-CON capacitors are used instead in
electrolitic ones. In designs in which tantalum capacitors are of
expected use, a close look to POSCAP is recommended. In either case,
improved conductance and better temperature behaviour is expected
over electrolitic and tantalum, respectively.
\item \textbf{FPGA}\\
FPGA connections are splitted in two pages: \textit{FPGA BANK} and
\textit{MGTX}.
With regard to \textit{FPGA BANK}, all I/O banks are powered to 3.3
volts, as previously indicated. Banks 0 and 1 hold clocking
resources, VME64x I2C connections, LEDs and some extra features.
Banks 2 and 3 plug all the pulses connections with no particular care
in the connections of the pins. This was a limitation in the
performance of V1, solved in V2. So as to much improve perfomance in
the clocked pulse repetition, \textbf{SerDes functionality} should be
used. By reading the advanced I/O resources guidelines from Xilinx,
connections should be done as in V2: \textbf{two non differential
input sources must not belong to \_P and \_N pins of a same
differential FPGA input.}\\
Obviously, clockless pulse repetition will have the lowest possible
jitter figure.\\
\item \textbf{White Rabbit clocking resources}\\
Just copied from SPEC project, V2 indepently configurable DAC
capability. All the decouplings are exactly the same as in SPEC.
\item \textbf{JTAG}\\
In this page the JATG connection, switches and external Flash memory is
depicted. External reset circuitry is added in V2.
\item \textbf{VME64X}\\
VME64X has two connectors P1 and P2. P1 is used for I2C communication
and P2 serves as a connection from front to rear: Blocking I/O
signals, rear LEDs, motherboard and piggyback IDs.\\
When attaching a V1 into a crate it can produce VME64x conflicts in
other VME64x boards, due to not daisy-chaining \textit{bus grant} and
\textit{interrupt ack} lines. This problem is solved in V2.
\item \textbf{INPUT UNIT}\\
The input unit uses an optocoupler preceeded by a DC rejection filter
(a differentiator). The line is terminated and protected via a TVS.
In V2 a Schimtt trigger is added right after the optocoupling to
sharpen the change of the signal.
\item \textbf{OUTPUT BLO}\\
BCT25244 is used because of two reasons:
\begin{itemize}
\item Powerful drive.
\item Reduce stocks cause it is already used in CTRs.
\end{itemize}
A net is misconnected in V1. Issue solved in V2.\\
An important feature implemented in the design is being
glitches-free. This is achived in different ways:
\begin{itemize}
\item Careful startup of the FPGA.
\item Placing of pull-ups or pull-downs in open enable pins.
\end{itemize}
\item \textbf{OUTPUT UNIT}
The output unit consist of a flyback
\end{itemize}
\subsubsection{Changes from V1 to V2}
While debugging V1, issues appeared.
\begin{itemize}
......@@ -285,11 +405,151 @@
\end{itemize}
\end{itemize}
\subsubsection{Modification to do on V2}
\begin{itemize}
\item \textbf{Power Supplies}\\
Change the Blocking power supply low resistor feedback to produce
Blocking pulses at 24V and not 21V:\\
Issues \textbf{679}
\end{itemize}
\subsection{Piggyback design}
CONV-TTL-RTM-BLO, namely CERN
\href{https://edms.cern.ch/nav/EDA-02453}{EDMS-02453 project}, is described
below.
\begin{itemize}
\item \textbf{TOP page}\\
It connects the VME64X P2 connector with the double row, one hundred
Semtech connector for the piggyback.\\
\item \textbf{Panel and Leds}\\
Just the connectors and nothing else. The TVSs are already in the
motherboard.
\end{itemize}
\pagebreak
\subsection{VHDL design}
The VHDL design has to achieve two milestones:
\begin{itemize}
\item \textbf{Basic functionality}\\
It covers the repetition of the pulse as in the previous legacy boards.\\
\item \textbf{Extended functionality}\\
It improves the basic functionality by time-tagging via White Rabbit the
pulses, allowing remote monitoring and reprogramming of the device.\\
\end{itemize}
\subsubsection{Basic functionality}
The basic functionality is covered in the design used for the
\textit{CONV-TTL-BLO V1} card installed in the test loop in PS
facilities.\\
The IP core has to:
\begin{enumerate}
\item Detect and replicated received pulses once they are not considered
as glitches.
\item Provide a safe and reliable working life. Not producing glitches at
startup.
\end{enumerate}
The IP core sampling frequency for the inputs is 200MHz. The internal
200MHz system clock is generated from the 125MHz clock. Then the induced
sampled jitter will be 5 ns.\\
The following table shows the configuration of the \textit{CONV-TTL-BLO V1}
board installed in the test sage loop in PS facilities:\\
\begin{table}[!htb]
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|R|}
\hline
\textbf{Parameter} & \textbf{Value}\\
\hline
\hline
Pulse height & 24 volts\\
\hline
Pulse length & 1 $\mu$s\\
\hline
Pulse rise time & 75 ns\\
\hline
Pulse fall time & 95 ns\\
\hline
Minimum repetition jitter & 5 ns\\
\hline
Channel LEDs blinking length & 250 ms\\
\hline
\end{tabularx}
\caption{Configuration for \textit{CONV-TTL-BLO V1} in PS safe loop test}
\end{center}
\end{table}
\subsubsection{Extended functionality}
\pagebreak
\section{RS485 boards replacement: CONV-TTL-RS485}
\subsection{Legacy boards}
\subsubsection{Use}
CONV-TTL-RS485 will be use as a more advance card that CONV-TTL-BLO. It
will be able to replicate pulses as in its Blocking counterpart and
redistribute GMT and timing information.\\
\subsubsection{Additional features}
With regard to legacy designs, CONV-TTL-RS485 will be able to detect
insuficient differential level in the reception lines. Thus, defective
and broken links can be detected.\\
\subsection{CONV-TTL-RS485 design}
\begin{itemize}
\item \textbf{TOP page}\\
The division of this project is the same as CONV-TTL-BLO. The driver
stage for outputting to the rear module has changed from Blocking to
RS485.\\
\item \textbf{Power Supply}\\
In this project the Blocking power supply has been removed. The line
filters added in CONV-TTL-BLO V2 have been added to CONV-TTL-RS485
V1.\\
The decoupling FPGA capacitors are the same and the external reset is
included in this page.\\
It should be remarked that all FPGA I/O banks are powered at 3.3
volts.\\
\item \textbf{FPGA BANK}\\
When CONV-TTL-RS485 was designed, the sampling jitter problem was not
found. Subsequently, a change in the I/O trigger FPGA pins for the pulse
repetition should be carried out in the same fashion as it was from
CONV-TTL-BLO V1 to V2.\\
\item \textbf{CLOCKS}\\
Two changes from CONV-TTL-BLO V1 have been done.\\
The first corresponds to let individual configuration of DACs from
the FPGA. The second is the use of cleaner power supply for the DACs.
Voltage drop in ferrites was measured and it is negligible.\\
\item \textbf{VME64X}\\
All the issues of bad daisy chaining in CONV-TTL-BLO V1 have been
addressed.\\
\item \textbf{MGTX}\\
A four position microswitch to enable network identification (which
accelerator/timing domain the card is attached to) is added to the
board.\\
\item \textbf{FRONT TTL}\\
The problems of missconnections and bad power supplying from
CONV-TTL-BLO V1 has been corrected in RS485. Same antiglitch features
applies for the pull-ups and pull-downs.\\
\item \textbf{FRONT PANEL}\\
In this page the new bicolour LED array was introduced, it works
together with Matthieu's IP core.\\
\item \textbf{INPUT UNIT}\\
By using same signed thresholds in the RS485 receivers, an bad/dead
link detection can be carried out.\\
\item \textbf{OUTPUT UNIT}\\
Same transceivers as in reception are used. They are compliant with
speed link for GMT replication.\\
\item \textbf{JTAG}\\
Changes needed in CONV-TTL-BLO V1 have been carried out here.\\
\end{itemize}
\pagebreak
\section{Rear Transition Module Motherboard}
The motherboard is shared between both the CONV-TTL-BLO and the
CONV-TTL-RS485. It provides connection to piggybacks from the VME64X P2
connector.
\subsection{CONV-TTL-RTM design}
The RTM motherboard consist of a VME64X P2 connector and a two rows 100 pin
male connector. The signals are bypassed from the P2 connector to the 100
pin connector and, for protection measures, TVS are included.
\pagebreak
\section{ELMA crate}
......@@ -328,4 +588,75 @@
Issue \textbf{537}
\end{itemize}
\pagebreak
\section{People involved in Level Conversion Circuits}
Success in a project is due to the joint work of a team. A list of all the
people involved in the project can be found in the table below.\\
I would like to take advantage of this line to thank them all again for
their help and work.\\
\begin{table}[!htb]
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|R|}
\hline
\multicolumn{2}{|c|}{\cellcolor{black}\textcolor{white}{\textbf{Design team}}}\\
\hline
\textbf{Erik Van der Bij} & Manager\\
\hline
\textbf{Matthieu Cattin } & Technical supervision - Installation\\
\hline
\textbf{Tomasz Wlostoski} & Technical help\\
\hline
\hline
\multicolumn{2}{|c|}{\cellcolor{black}\textcolor{white}{\textbf{Installation
- operators}}}\\
\hline
\textbf{Claude Dehavay } & Installations manager\\
\hline
\textbf{Emmanuel Said } & Main Blocking/RS485 installator - cabling -
front/rear panel\\
\hline
\textbf{Olivier Barriere} & Installation - front/rear panel\\
\hline
\hline
\multicolumn{2}{|c|}{\cellcolor{black}\textcolor{white}{\textbf{ELMA
crate}}}\\
\hline
\textbf{Magnus Bjork } & ELMA crate CERN's responsible\\
\hline
\textbf{Boehr Timo } & ELMA crate links\\
\hline
\textbf{Frank Weiser } & ELMA crate links\\
\hline
\textbf{Silviu Bodeanu } & ELMA System Monitor responsible\\
\hline
\textbf{Mihai Savu } & ELMA I2C C developer\\
\hline
\hline
\multicolumn{2}{|c|}{\cellcolor{black}\textcolor{white}{\textbf{DEM}}}\\
\hline
\textbf{Betty Magnin } & Manager for PCB design and manufacturing\\
\hline
\textbf{William Billereau} & Manager for PCB design and manufacturing\\
\hline
\textbf{Benoit Civel } & Responsible for layout in
\textit{CONV-TTL-BLO V1}\\
\hline
\textbf{Claude Andouillet} & Responsible for layout in
\textit{CONV-TTL-RTM},\textit{CONV-TTL-RTM-BLO}
and \textit{CONV-TTL-RTM-RS485}\\
\hline
\textbf{Bruno Recoldon } & Responsible for layout in
\textit{CONV-TTL-BLO V2} and
\textit{CONV-TTL-RS485}\\
\hline
\end{tabularx}
\caption{People involved in the project}
\end{center}
\end{table}
\end{document}
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