Conv TTL Blocking issueshttps://ohwr.org/project/conv-ttl-blo/issues2019-02-12T09:59:38Zhttps://ohwr.org/project/conv-ttl-blo/issues/21[BLO-V2] Silkscreen for T10, T11, T122019-02-12T09:59:38ZTheodor-Adrian Stana[BLO-V2] Silkscreen for T10, T11, T12The silkscreen for T10, T11 and T12 is flipped. To compare, see the rest
of the channels vs. the area highlighted in red
below:
![](/uploads/1b112651937764214c391795183a6f07/tranny-silkscreen.png)
This should be fixed in the eventuality of a V3 board.
### Files
* [tranny-silkscreen.png](/uploads/1b112651937764214c391795183a6f07/tranny-silkscreen.png)Denia Bouhired-FerragDenia Bouhired-Ferraghttps://ohwr.org/project/conv-ttl-blo/issues/22[BLO-V2] Displacement of J3 connector2019-02-12T09:59:39ZTheodor-Adrian Stana[BLO-V2] Displacement of J3 connectorConnector J3 is placed too close to the piggyback side, thus bending the
rear panel when it is placed. This bending means that one has to apply
force to the front panel when mounting it; this added to potential
forces exerted on the J3 connector when operators connect wires to the
rear panel, might lead to wearing out connector J3 on the long term.
Thus, connector J3 should be displaced by ~3mm from the rear panel
(i.e., towards the VME connector side).Theodor-Adrian StanaTheodor-Adrian Stanahttps://ohwr.org/project/conv-ttl-blo/issues/23[BLO-V2] Add measurement on blocking outputs2019-02-12T09:59:40ZProjects[BLO-V2] Add measurement on blocking outputsAdd measurement on blocking outputs, just before the connector.
In order to be able to tell our users that the pulse is going out of the
module.https://ohwr.org/project/conv-ttl-blo/issues/24[BLO-V2] Front panel pulse LED leads too long2019-02-12T09:59:40ZTheodor-Adrian Stana[BLO-V2] Front panel pulse LED leads too longThe leads for the TTL pulse LEDs are too long and can touch the EMC
shielding strip at the base of the ELMA crate, causing a short circuit
across the LED. This occurs only when the board is introduced in the
first slot of the crate and does not destroy the LED, it only prevents
it from functioning properly.
For now, the issue will be fixed by sending a memo to the assembly
company to cut the leads as short as possible. In V3, the possibility of
replacing the TTL pulse LEDs with SMD LEDs should be investigated.
Alternatively, one could try to place the LEDs further away from the
front panel, avoiding contact with the EMC strip.Denia Bouhired-FerragDenia Bouhired-Ferraghttps://ohwr.org/project/conv-ttl-blo/issues/25[BLO-V2] No silkscreen on blocking outputs2019-02-12T09:59:42ZTheodor-Adrian Stana[BLO-V2] No silkscreen on blocking outputsThe blocking output circuitry on the boards can be better marked by
delimiting it with, e.g., silkscreen rectangles. This would aid
debugging the board.
The issue can be solved as part of V3 boards.Denia Bouhired-FerragDenia Bouhired-Ferraghttps://ohwr.org/project/conv-ttl-blo/issues/26[BLO-V2] Add protection for blocking output stage2019-02-12T09:59:43ZTheodor-Adrian Stana[BLO-V2] Add protection for blocking output stageWith a wrong firmware downloaded to the FPGA, the blocking output stage
can be destroyed by forcing a logic HIGH on the FPGA output.
Continuously turning on the controlling MOSFET would create a high
current which burns up this transistor. Since one FPGA output drives
three blocking outputs (three outputs per channel), this issue extends
to three burnt transistors.
The issue should be solved as part of V3 boards by implementing a
protection circuit.https://ohwr.org/project/conv-ttl-blo/issues/27[BLO-V2] Add VME Interface2019-02-12T09:59:44ZTheodor-Adrian Stana[BLO-V2] Add VME InterfaceThe VME interface on the backplane can be connected to from the board.
This issue can be solved as part of a possible V3 and would add to the
capabilities of pulse converter boards.https://ohwr.org/project/conv-ttl-blo/issues/28[BLO-V2] Confusing net names2019-02-12T09:59:45ZTheodor-Adrian Stana[BLO-V2] Confusing net namesSome of the net names in *U\_InputBlocking.SchDoc* are confusing. An
example of the issue, which should be solved in V3, is given in the
figure
below:
![](/uploads/2b5a85c00850a68c3cf209d5bd28a668/confusing-net-name.png)
The data line from the EEPROM to the FPGA should also be changed, to
follow the usual SPI net names (MISO, MOSI).
The *full* list of net names that should be changed are:
<table>
<tbody>
<tr class="odd">
<td><b> Net name </b></td>
<td><b> Change to </b></td>
</tr>
<tr class="even">
<td>FPGA_BLO_IN_1_N</td>
<td>FPGA_BLO_IN_6_N</td>
</tr>
<tr class="odd">
<td>FPGA_BLO_IN_2_N</td>
<td>FPGA_BLO_IN_5_N</td>
</tr>
<tr class="even">
<td>FPGA_BLO_IN_3_N</td>
<td>FPGA_BLO_IN_4_N</td>
</tr>
<tr class="odd">
<td>FPGA_BLO_IN_4_N</td>
<td>FPGA_BLO_IN_3_N</td>
</tr>
<tr class="even">
<td>FPGA_BLO_IN_5_N</td>
<td>FPGA_BLO_IN_2_N</td>
</tr>
<tr class="odd">
<td>FPGA_BLO_IN_6_N</td>
<td>FPGA_BLO_IN_1_N</td>
</tr>
<tr class="even">
<td>FPGA_PROM_DIN</td>
<td>FPGA_PROM_MISO</td>
</tr>
</tbody>
</table>
### Files
* [confusing-net-name.png](/uploads/2b5a85c00850a68c3cf209d5bd28a668/confusing-net-name.png)https://ohwr.org/project/conv-ttl-blo/issues/29[BLO-V2] Decoupling capacitor connections wrong2019-02-12T09:59:45ZTheodor-Adrian Stana[BLO-V2] Decoupling capacitor connections wrongTwo decoupling capacitors have the to ground missing. Capacitors C110
and C130 have their pins connected together, but not also to ground, as
they should be. The figure below illustrates the
error:
![](/uploads/d6ebb157abf193c5ed7a1460d10449cf/cap-err.png)
This issue should be corrected in V3 boards, if they shall be produced.
### Files
* [cap-err.png](/uploads/d6ebb157abf193c5ed7a1460d10449cf/cap-err.png)Denia Bouhired-FerragDenia Bouhired-Ferraghttps://ohwr.org/project/conv-ttl-blo/issues/30[BLO-V2][RTMM] Changes to front and rear panels' design and assembly documents2019-02-12T09:59:46ZTheodor-Adrian Stana[BLO-V2][RTMM] Changes to front and rear panels' design and assembly documentsThe EMC gaskest on top of the front and rear panels (BLO & RTMM boards)
appear in the assembly document as one single item: *EMC Front Panels -
Aluminium With EMC Gasket acc. IEEE - Thickness 2.5mm*, with
manufacturer P/N *66-518-26*. As was the case in issue \#660 with the
SVECs, the gaskets are sold separately from the crate. Thus, they should
appear as separate items in the assembly document.
The front panel design file in EDMS also contains a no-longer-valid kit
number (26D604-6). This should be removed from the front panel drawing.
The following changes should be made (*EDA-02446*):
- Ref. 1: *EMC Front Panel Aluminium with EMC Gasket acc. IEEE* -\>
*EMC Front Panel Alumniniun acc. IEEE*
- Ref. 1: Change *Observations* to *Thickness 2.5mm*
- add *ELMA 81-062-06* gaskets to the *arrangement* document
- remove kit 26D604-6 from front panel drawing
The SVEC design should be used as a reference for the *arrangement*
document:
https://edms.cern.ch/file/1249647/3/EDA-02530-V2-0_arrangement-mat.pdf
A similar issue exists with the RTMM boards. The EMC gaskets are however
properly included in the *arrangement* document of these boards.
The changes that should be made here are(*EDA-02452-V2-0*,
*EDA-02452-V2-1*):
- Ref. 1: *EMC Front Panel Aluminium with EMC Gasket acc. IEEE* -\>
*EMC Front Panel Alumniniun acc. IEEE*
- Ref. 1: Change *Val & Device* column for first entry to *6U-8HP*
- Ref. 1: Change *Observations* field for first entry to *Thickness
2.5mm*
- Ref. 5, 6 (injector/ejector handles): Change *Description* field to
*Top/Bottom Black Handle **without** ESD Pin and Red button*Theodor-Adrian StanaTheodor-Adrian Stanahttps://ohwr.org/project/conv-ttl-blo/issues/31[BLO-V2] Mainboard power-on reset circuit has long timing constant2019-02-12T09:59:48ZTheodor-Adrian Stana[BLO-V2] Mainboard power-on reset circuit has long timing constantThe POR circuit on the BLO converter mainboards have 24.2s time
constants. This POR circuit is only used for resetting the internal FPGA
logic. The issue should be fixed in V3 by either:
\- lowering the time constant (100ms should be a good starting point),
or
\- changing it with a button reset circuit, or
\- removing it altogether and relying on internal logic reset from a
counter implemented in VHDL.
In the meantime, reset will be generated using a counter, similar to the
V1 implementation, where a POR reset circuit was not included.Theodor-Adrian StanaTheodor-Adrian Stanahttps://ohwr.org/project/conv-ttl-blo/issues/32[RTMP-BLO/RS-V1] RTMP detection wrong in V1 panels2019-02-12T09:59:50ZTheodor-Adrian Stana[RTMP-BLO/RS-V1] RTMP detection wrong in V1 panelsAn issue exists in the RTMP detection, both for blocking and RS-485
RTMPs. The bug will be investigated in the Altium project, it seems to
be a net label substituted for a net comment in the schematics; the
certain thing is that all three RTMP detection pins are **open** on V1
RTMPs, both blocking and RS-485.
This issue will be solved by redefining the [RTM detection
scheme](https://www.ohwr.org/project/conv-ttl-blo/wikis/RTM-board-detection).Theodor-Adrian StanaTheodor-Adrian Stanahttps://ohwr.org/project/conv-ttl-blo/issues/33[BLO-V2] Front panels should be the same as for RS-485 converters2019-02-12T09:59:51ZTheodor-Adrian Stana[BLO-V2] Front panels should be the same as for RS-485 convertersThe front panel designs for the Blocking front modules are not the same
as for the RS485 converter boards. The difference between the two is
that the front panel for BLO-V2 boards have round cuts for each of the
bicolor LEDs, while the RS485 have one rectangular cut for each of the
bicolor LED rows. This is not a bug, since the round cuts are
appropriately made, but the design should be the same as for the RS485,
with the rectangular
cuts.
![](/uploads/28e10d7d752c2f4aef355a9ecb07f604/blo.png)
![](/uploads/e1ccc3e089809055581f102f559a095a/rs.png)
### Files
* [blo.png](/uploads/28e10d7d752c2f4aef355a9ecb07f604/blo.png)
* [rs.png](/uploads/e1ccc3e089809055581f102f559a095a/rs.png)Theodor-Adrian StanaTheodor-Adrian Stanahttps://ohwr.org/project/conv-ttl-blo/issues/34[RTM-V2] Different RTM detection lines for the V2 boards2019-02-12T09:59:52ZTheodor-Adrian Stana[RTM-V2] Different RTM detection lines for the V2 boardsV2 boards should have a different RTM detection pattern than V1 boards.
Advised to use the next empty line in the RTM detection table listed
[here](https://www.ohwr.org/project/conv-ttl-blo/wikis/RTM-board-detection).Theodor-Adrian StanaTheodor-Adrian Stanahttps://ohwr.org/project/conv-ttl-blo/issues/35[RTM-V1] Project link incomplete or wrong on silkscreen2019-02-12T09:59:52ZTheodor-Adrian Stana[RTM-V1] Project link incomplete or wrong on silkscreenFor the RTM boards (used in both BLO and RS485 converters), there is
only the link to the BLO board projects
(https://www.ohwr.org/project/conv-ttl-blo). This should be fixed in one
of two ways:
1\. list only ohwr.org
2\. list both the ttl-blo and ttl-rs485 projects on the silkscreen.https://ohwr.org/project/conv-ttl-blo/issues/36[RTMP-V1] Wrong project reference number on piggyback front panel2019-02-12T09:59:53ZTheodor-Adrian Stana[RTMP-V1] Wrong project reference number on piggyback front panelThe project reference number on the piggyback front panel is wrong. It
is referring to EDA-02452 (RTM motherboard), when it should be in fact
referring to EDA-O2494-V2.https://ohwr.org/project/conv-ttl-blo/issues/37[RTM-V1] Guard traces between differential lines2019-02-12T09:59:53ZTheodor-Adrian Stana[RTM-V1] Guard traces between differential linesA potential signal integrity issue might exist on the V1 RTMs. Long
guard traces connected to ground in few places exist between the signal
lines leading to the piggybacks. Due to their length and width, they can
create antennae, leading to unwanted noise in the signal.
This issue should be resolved in the PCB design of V2.https://ohwr.org/project/conv-ttl-blo/issues/38[BLO-V2] No LEDs on INV-TTL inputs2019-02-12T09:59:54ZTheodor-Adrian Stana[BLO-V2] No LEDs on INV-TTL inputsThe inverted TTL inputs on the blocking converter boards have no
signaling LEDs mounted on them. This issue should be taken care of in
V3.Denia Bouhired-FerragDenia Bouhired-Ferraghttps://ohwr.org/project/conv-ttl-blo/issues/39[BLO-V2] Do not mount push button PB12019-02-12T09:59:55ZCarlos Gil Soriano[BLO-V2] Do not mount push button PB1The push button should be not mounted in V2.1. A note shall be made on
this in the schematics and BOM (?).Theodor-Adrian StanaTheodor-Adrian Stanahttps://ohwr.org/project/conv-ttl-blo/issues/40[BLO-V2] Blocking pulse is 21V instead of 24V2019-02-12T09:59:56ZCarlos Gil Soriano[BLO-V2] Blocking pulse is 21V instead of 24VThe Blocking is outputted with an amplitude of 21V. To resolve this
problem, the low feedback resistor in the power supply of the Blocking
should be decreased.
Resistor R251, which has a value of 510R, is wrong. Instead, use a
resistor of 330R.
This error was probably due to not having reported back this change as
an issue in the OHWR page.Theodor-Adrian StanaTheodor-Adrian Stana