Pulldown resistors on TTL outputs
On the Schematics page 13, the FPGA_OUT_TTL [1:6] and INV_OUT[1:4] should all have pulldown resistors.
Indeed, as it has been shown in issue #1104, where identical circuitry is used to enable the pulsing BLO output, leaving the FPGA outputs in high-impedance state (input to buffers), can cause the buffer to output a High level, if it is enabled accidentally (during hot swap for example as in issue #1104).
Although the TTL outputs will not be damaged in the same way as the blocking ones, it is however good practice to keep such signals at ground level until they are driven by the FPGA.