[BLO-V2] Confusing net names
Some of the net names in U_InputBlocking.SchDoc are confusing. An example of the issue, which should be solved in V3, is given in the figure below:
The data line from the EEPROM to the FPGA should also be changed, to follow the usual SPI net names (MISO, MOSI).
The full list of net names that should be changed are:
Net name | Change to |
FPGA_BLO_IN_1_N | FPGA_BLO_IN_6_N |
FPGA_BLO_IN_2_N | FPGA_BLO_IN_5_N |
FPGA_BLO_IN_3_N | FPGA_BLO_IN_4_N |
FPGA_BLO_IN_4_N | FPGA_BLO_IN_3_N |
FPGA_BLO_IN_5_N | FPGA_BLO_IN_2_N |
FPGA_BLO_IN_6_N | FPGA_BLO_IN_1_N |
FPGA_PROM_DIN | FPGA_PROM_MISO |