Frequently Asked Questions
Q. My hwvers register is showing all zero's. Which version is my board?
PCB/HW version recognition is a new hardware feature in v4.0 boards. If
your hwvers register field is showing all zeros, it means your board is
version 3 or earlier.
In effect this means that your board cannot handle frequencies higher
than 4.16kHz and only outputs pulses 1.2us wide.
Q: What are the on-board switches for?
Switch | Description |
---|---|
SW1.1 | Glitch filter enable (see Section 4.5 of the user guide) |
ON - glitch fillter enabled, output jitter present | |
OFF - glitch filter disabled, no output jitter (default) | |
SW1.2 | Pulse width select (see Section 4.3 of the user guide) |
ON - short pulse width [250 ns] | |
OFF - long pulse width [1.2 us] (default) | |
SW2.4 | TTL/TTL-BAR selection switch (see Section 4.2 of the user guide) |
ON { TTL channels receive and generate TTL (default) | |
OFF { TTL channels receive and generate TTL-BAR |
Q: What is the maximum input pulse width ?
On blocking channels, 4.8 us. Pulse widths longer than this value may damage the blocking input circuitry (mainly, the optocoupler).
On TTL channels, anything up to the limit pulse period. The idea here is to have a pulse, so that the FPGA circuitry notices the rising edge and generates a pulse.
Note that whatever the input pulse width, the output pulse width will be either 1.2 us or 250ns depending on the board version (and the selected pulse width), see following question.
Q: How wide are output pulses?
In PCB version 2.1 of the board (and prototyping version 3) output pulse width is set to the nominal 1.2 us.
Version 4 boards add a pulse width selection option. The selection is done via dip switch SW1.2 on the board:
- Switch OFF position gives a LONG, 1.2us-wide pulse.
- Switch ON position gives a SHORT, 250ns-wide pulse.
Note*: In practice, this pulse width limitation is done in gateware. Only gw release v4.0 supports pulse width selection. this version remains backwards compatible with all versions of the board and is able to activate and deactivate this option depending on the PCB version.
Q: What is the difference between repetition frequencies in the continuous and in the burst mode?
- The continuous mode frequency limit, means the frequencies up-to which repetition is guaranteed continuously.
- The burst mode offers much higher frequency limits than those
offered by the continuous modes. However these frequencies are only
supported by a limited amount of time.
Once the pre-definened (Embedded in the FPGA) times (associated with burst mode frequencies) have ellapsed, the board will start missing pulses.
Q: My board is missing pulses, why?
On-board diagnostics may help in defining the source of the problem.
There are two types of error flags associated with missing pulses:
- flim_err: frequency limit errors mean that the maximum frequency allowed for a given pulse-width has been surpassed. Table below summarises these limits:
Board version | SW1.2 | Pulse width | Max Freq |
---|---|---|---|
v2.1-v3 | ON/OFF | 1.2µs | 4.16kHz |
v4.0 | ON | 250ns | 2MHz |
v4.0 | OFF | 1.2µs | 104kHz |
To resolve this error, the correct frequency (below specified limits) must be input.
-
fwdg_err: Frequency watchdog errors mean that the board has
been requested to repeat frequencies for longer that it can support.
Check the supported repetition times Vs
frequency
for more information. In this situation, the board lowers its
repetition frequency dynamically in order to protect the output
circuitry from irreversible damage.
To resolve this, repetition freqency must be lowered, ideally allowing the board some cool-off time (10s to be safe) before error-free repetition can resume, of course, within board frequency limit specifications.
In both cases, error flags (and error LEDs) can be cleared remotely or via a power reset.
Q: What is the maximum input frequency?
This will depend on the version of the board you are operating, as well as on the pulse width selected.
- v3.0 and earlier:The input frequency of pulses should not be higher than 4.150 kHz. CONV-TTL-BLO boards have pulse rejection logic implemented inside the FPGA, that limit the pulse duty cycle to 1/200. This is to protect the blocking output circuitry.
- v4.0 of the board: AS the burst mode is activated, the maximum achievable pulse frequencies depend on output pulse-width selected. The follwoing table summarises frequency limits.
Board version | SW1.2 | Pulse width | Max freq in continuous mode | Max Freq. in burst mode |
---|---|---|---|---|
v2.1-v3 | ON/OFF | 1.2µs | 4.16kHz | N/A |
v4.0 | ON | 250ns | 571kHz | 2MHz |
v4.0 | OFF | 1.2µs | 52kHz | 104kHz |
See the CONV-TTL-BLO user guide, chapter "Pulse repetition frequency" for more details.
Q: How many channels does a TTL to blocking pulse converter system have?
Six pulse conversion channels. Each channel has one TTL output and three blocking outputs.
On any channel, you can input and output any combination between TTL and blocking:
- TTL input to TTL output
- TTL input to blocking output
- Blocking input to TTL output
- Blocking input to blocking output
Flip the TTL switch (SW2.4) on the board and you can use the board exclusively with TTL-BAR:
- TTL-BAR input to TTL-BAR output
- TTL-BAR input to blocking output
- Blocking input to TTL-BAR output
- Blocking input to blocking output
Additionally, you also have four general-purpose inverter channels on the front panel. These can be used to invert a signal locally, without having to remove the board from the rack.
As an example, if your TTL switch is set to TTL signals and you need to repeat/convert a TTL-BAR signal, you don't need to remove the board from the rack, flip a switch and plug it back. You can use one of the INV-TTL channels to reverse the polarity of the TTL-BAR signal and use it to your will. Bear in mind that if you want to repeat this TTL-BAR signal, you need to use another INV-TTL channel to reverse the polarity the CONV-TTL-BLO is outputting, since the CONV-TTL-BLO will output TTL signals.
Q: How do I know if an RTM is correctly connected to the rear for the VME backplane?
There is a memory register that signals if an RTM is connected and what
type it is. For conv-ttl-blo boards, the RTM lines indicated the version
of the blocking RTM connected.
Other RTM information will apply to other types of RTMs such as the ones
that plug into the sister-board
conv-ttl-rs485.
Have a look at the description of RTM detection
lines to find out more about your
RTM.
Q: Can I obtain more than three blocking signals out of a single one?
*It is possible, but given high current consumption of blocking outputs, a limit of active blocking outputs per crate is imposed*
Within these limits, it is possible to obtain more than 3 blocking outputs from a single input. An example of this is covered in Appendix B.2 of the CONV-TTL-BLO user guide. You can form a daisy-chain on the front panel using the TTL channels, and use the blocking outputs of each channel to repeat your signal. Like this, you can repeat one blocking signal into a maximum of 18. Keep in mind there is a delay of 80 ns associated with each channel.
Should you want to repeat one TTL signal into more, you can do the exact same thing in reverse; input a TTL signal on a channel, and use the blocking channels to make a daisy-chain. You can use this technique to replicate one TTL signal into a maximum of six TTL signals and thirteen blocking signals. Keep in mind there will again be a delay of 80 ns on each channel.
Note that if you daisy-chain the INV-TTL outputs, you might get glitches on startup, due to a delay in the signal chain. It is therefore not recommended to daisy-chain INV-TTL outputs.*
Q: Are the input and output lines terminated?
The input lines on both TTL and blocking signals are terminated with 50-ohm resistors. The output lines are not terminated.
Q: Can I uses LVTTL input levels?
Yes, the TTL input is made of a parallel 50 Ohm termination and a SN74LVC14AD Schmitt trigger inverter. The inputs are compatible to TTL and LVTTL input levels.
Q: What to do to have a low jitter?
When needing a low jitter on the output signal, just make sure that SW1.1 is set in the position OFF (User Guide, pages 16 and 26-27). With this (default) setting the signal chain is fully combinatorial. The jitter is then virtually 0, and negligible compared to the Blocking level signal rise times of 75ns or more.
Q: Why is a TTL-BAR pulse generated when an upstream card powers down?
This is a natural effect with TTL-BAR. Since TTL-BAR is an active-low pulse, and therefore the idle state is high, when an upstream node powers down, the TTL-BAR input goes low, and this gets interpreted by the CONV-TTL-BLO as a pulse.
The effect cannot be mitigated, but in any case crates should not power down under normal operation.
Note that this effect only occurs under TTL-BAR pulse repetition. TTL pulse repetition is not affected.
Q: Why is a TTL-BAR pulse generated when I remove a wire from the TTL input?
Similar to the question above, a pulse gets generated because we have a 50-ohm termination to chassis ground, and this termination acts as a pull-down on the channel when a cable is not plugged in. When a cable which carries an idle-high signal gets removed, the 50-ohm termination pulls down the line to chassis ground, and this again gets interpreted as a pulse on the input.
A pulse may also get generated when a the cable is plugged into the board due to the fact that glitches are created due to imperfect mechanical contact between the cable conductor and the connector as the cable is plugged in. Note that even with the glitch filter enabled, this effect is not fully removed.
By making sure no cables are removed or plugged in while the board is in operation, this effect will not appear.
Note that this effect only occurs under TTL-BAR pulse repetition. TTL pulse repetition is not affected.
Q: What is MultiBoot? What is a typical MultiBoot sequence?
MultiBoot is described here.
The typical sequence a user should run through when uploading is the following:
- Get the latest release gateware version from here
- Run MultiBoot to update the gateware to flash address 0x170000 this latest release (use for example software/multiboot/multiboot.py from the repository)
- Check that the updated gateware is the expected one, by reading the gateware version from the board's SR at address 0x4
Should you want to check which golden gateware version you have, run the following steps:
- Run MultiBoot from a wrong address (e.g., 0x180000), without writing a new bitstream to the flash
- This boots back to the golden gateware version, which you should check is the latest (by reading the SR at address 0x4) against this webpage
- Power-cycle the ELMA crate to boot back to the latest release gateware
Maciej Suminski, Denia Bouhired, July 20th, 2017
Theodor-Adrian Stana, Erik van der Bij, 23 July 2015