CONV-TTL-BLO project
Project Description
The TTL to blocking converter is a system designed to replicate TTL and blocking pulses. An incoming TTL pulse is replicated simultaneously on both the TTL and blocking channel on which it was received. Similarly, a blocking pulse on an input channel is replicated on both blocking and TTL outputs of the same channel. The system consists of two VME64x double height boards, the front module and the rear transition module (RTM). The front module contains all the active circuitry, whereas the RTM is passive and targeted for connectivity.
Main Features
- VME64x double-height form factor using front and rear transition module (RTM)
- The output pulse is a CERN level standard, blocking standard
- Support for high frequency bursts.
- Selectable pulse width resulting in different repetition
frequencies:
- 1.2 us enables continuous repetition for frequencies up to ~52kHz and burst mode support for frequencies up to ~104kHz.
- 250 ns enables continuous repetition for frequencies up to ~571kHz and burst mode support for frequencies up to 2MHz.
- Six conversion and replication channels. Each channel is capable of
replicating:
- TTL to TTL (front panel)
- TTL-BAR to TTL-BAR (front panel)
- TTL to blocking (front panel to rear panel)
- Blocking to TTL (rear panel to front panel)
- TTL-BAR to blocking (front panel to rear panel)
- Blocking to TTL-BAR (rear panel to front panel)
- Blocking to blocking (rear panel to rear panel)
- Four additional general-purpose inverter channels at the front
panel, useful for converting:
- TTL to TTL-BAR
- TTL-BAR to TTL
- LEMO 00 connectors at both front and rear panels. FPGA isolated from input lines
- Galvanic isolation on the blocking outputs
- Rear panel: input protection against high-current and high-voltage transients
- Communication through I2C on the VME bus. I2C bus available on ELMA
crates
- Diagnostics
- Converter board ID
- Unique board ID
- Gateware version
- On-board switches and RTM lines status (RTM Detection)
- Input pulse counters
- Input pulse time-tagging
- Remote reset
- Manual pulse triggering
- System errors
- Remote reprogramming
- Diagnostics
- LEDs:
- One pulse LED for every channel, front and rear panels
- Various status LEDs on the front panel (White Rabbit, multicast, power, error, etc.)
Important notes
- Currently does not implement the VME interface. VME backplane used for power supply levels and I2C communication
- Hardware for White Rabbit protocol support available (oscilators, SFP connector, LEDs), but functionality is not implemented inside the FPGA.
Project Information
This project is divided into three separate projects:
Useful user documentation can be found at these locations:
- Getting started with CONV-TTL-BLO boards
- User guide
- CERN-specific information
- Frequently Asked Questions
Status
Date | Event |
---|---|
02-03-2011 | Stock manager worries about low stock of LA-TTL-BLO modules. |
01-07-2011 | Start working on project. |
12-09-2011 | Functional Specifications Draft proposed |
20-09-2011 | Blocking standard defined. |
24-02-2012 | 3 prototypes ordered for 30-03-2012. |
05-04-2012 | Prototypes received. Testing HDL simple repetition code. |
21-11-2012 | Deployed a Blocking V1 in PS facilities. Source and bitstream available here |
10-12-2012 | Will build 4 V2's before building another 20 and after that 100. Ordered 25 RTM modules. |
08-01-2013 | Received 4 V2 boards. Some assembly problems on two. |
18-02-2013 | Order placed for 25 RTM and 27 BLO-RTMP boards. |
15-03-2013 | 25x RTMs and 27x BLO-RTMPs received |
05-06-2013 | 25 CONV-TTL-BLO boards and front panels produced. |
19-06-2013 | 10 rear panels produced. |
10-09-2013 | Received 15 more rear panels. |
11-09-2013 | Test system set up in LINAC 4 facility (see testing page for more information). |
09-10-2013 | Ordering 100 sets. |
15-11-2013 | Design review held (see design-review-2013 branch) |
20-12-2013 | Received 100 front module boards. |
09-01-2014 | Added 100 front modules to stock. |
12-02-2014 | Received 100 produced and assembled RTMs. |
10-03-2014 | CONV-TTL-BLO now with diagnostics support. |
09-04-2014 | Gateware v2.1 released |
15-04-2014 | Gateware v2.2 released |
26-09-2014 | Gateware v3.0 released |
08-02-2016 | Reviving the test system and studying Issue 1104 |
01-07-2016 | Schematics, layout and front panel modification requests sent to DEM for V3 |
05-08-2016 | EDA-02446-V3-0 Ready for release. Order placed for 3 prototypes. Components ready |
26-10-2016 | EDA-02446-V3-0 Three boards received. Outputs give unexpected overshoot. Will need a V4 |
03-02-2017 | EDA-02446-V4-0 Review held |
14-02-2017 | Updated user manual and hardware design guide for v4 boards |
8-03-2017 | v4 schematics, PCB layout, mechanical parts and manufacturing information available in EDMS |
10-03-2017 | Gateware v4.0 released |
20-03-2017 | 5 prototypes ordered of v4.0 boards, expected from 15-05-2017 |
12-06-2017 | 5 v4 prototypes have been received, small error on silkscreen leads to issue #1611 |
13-09-2017 | Schematics v4-1 released on EDMS to resolve issue #1611 |
16-10-2017 | Prototypes with new firmware successfully running on installations. Error-free since July 20th. Launch of large scale production. 460 motherboards and 405 RTM modules |
23-01-2018 | Gateware v4.1 released |
20-07-2018 | pre-series of 25 v4.1 boards have been delivered to CERN |
15-08-2018 | 405 boards of CONV-TTL-RTM-BLO, EDA-02453 v3.2 delivered at CERN |
Theodor-Adrian Stana, Carlos Gil-Soriano, Erik van der Bij, Denia Bouhired-Ferrag - August 23rd, 2018