PCB Review Notes 20-01-2012
Assistants: Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski, Carlos Gil Soriano.
Schematics
- All ICs must have the inputs in a known state: IC2b IC10c, IC11E/F.
Check others.
- DONE: now every IC has known inputs.
- Unused inputs should be directly connected to GND or power.
- DONE: now every IC has known inputs.
- Some pins are connected to GND or Power through pulls
- DONE: in IC1A, IC1B inputs
- REJECTED: in IC1A, IC1B, IC2A outputs (antiglitch feature).
- Change 470K pullup resistor in TPS3808G01DBVT for something stronger
- REJECTED: in the datasheet they specify that the pullup shouldn't be less than 10K and in the circuit example they are using 1M. Not changed.
- Add one 47uF tantalum capacitor for every channel
- DONE Possible zigzagging is fine on top layer.
- Manual control over Blocking Power Source
- DONE: it doesn't need external pullup due to internal one in TPS3808G01DBVT
- Change 100 Ohm pull-ups for something less strong: IC3, IC1,...
- DONE
- 50 Ohm input termination must be mounted in front board, not in rear
board.
- DONE
- Ground IN- of FOD060L.
- DONE
- Change FOD060L from another pin-to-pin compatible.
- DONE: changed to HCPL-0601
- J12 should be changed for a header. Nets should directly connect
with FPGA.
- DONE
- Add glitch-free controll from FPGA to MR_N pin of Blocking PS
enable IC.
- DONE
- Add inverted to the output of TPS3808G01DBVT to connect it to
TPS40210DGQ
- DONE: now in IC11E
- Recheck antiglitch
- DONE: move from LS to HC. Replacement of AND gate for NAND gate. Changed pull-ups.
- CONSIDERING: really necessary an external debouncer?
Layout
- P3V3_VME more poly on Top Layer.
- TOP LAYER
- Mismatching in names.
- Remove CERN logo.
- SILKSCREEN TOP
- Add project URL + license.
- SILKSCREEN TOP
- P5V_VME and VME P2_5V not used: to remove.
- BOTTOM LAYER
- L4PWR
- Silk for J12
- SILKSCREEN TOP: add "DEBUG GPIOs"
- Silk for SW1
- SILKSCREEN TOP: add "TTL (up) TTLbar (down)" in pin 8.
- Gather all clocking together
- TOP LAYER: Pin swapping of FPGA_CLK_[x] and move it up
- Possibly rotate 24V and do bigger some power net (1V2,MGBT) thanks
to the two power planes.
- L5PWR: it will be used for 24V. Make it bigger. 24V can be extended to the edge board.
- L4PWR: Used for 1V2, FPGA_MGTAVCC.
- L4PWR: Move 1V2 from L5PWR to L4PWR and make it bigger.
- L4PWR: Make FPGA_MGTAVCC bigger.
- Add more vias to 24V domain
- TOP LAYER: add more near C38, C39
- L7GND uses
- L7GND: it will be mainly used for grounding the 24V domain (lower part with the transformers).
- L2GND uses
- L2GND: can be used to ground FPGA
- FPGA_MGTAVCC put at least 5x100nF to MGTAVCC, like in SPEC
- REJECTED: in this design only half of the Dual Tiles are used (only 101), so half of the supplies are tied to ground as specified by Xilinx. Then, it is not possible to place more caps.
- FPGA_MGTAVCC one BGA via is not connected to power net
- L4PWR one extra 100nF can be added check FPGA_MGTAVCC net vias.
- Move inside MGBT capacitors.
- FPGA_CLK can be pin swapped.
- TOP LAYER Move it up, preferrably
- Test points should not be mounted by default.
- Add extra GND test points all around the board.
- TOP LAYER
- SFP rx/tx can be routed on top layer.
- TOP LAYER
- Remove copper islands.
- VERY IMPORTANT: remove plugged in holes.