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Conv TTL Blocking
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Conv TTL Blocking
Last edited by
OHWR Gitlab support
Mar 27, 2019
Stock manager worries about low stock of
Start working on project.
Review of architecture
Blocking level output circuit simulated. Will be documented.
Blocking Oscillator documentation
Blocking Oscillator prototype made, problems integrating into CTDAH. Moving to a flyback solution.
Blocking Oscillator Daisy-chain alternatives document
. Prototype board already made, waiting for LM2733
Functional Specifications Draft proposed
The flyback module that outputs the blocking signal works fine.
PF0552.104NL transformer samples were received. Pulse Converter Unit works nicely.
Schematics draft done. See:
CTDAH - White Rabbit capable version up in repo (CTDAHalt). Moving to HDL.
Second Review of architecture. Modifications accomplished to CTDAHalt
Uploaded package containing files for
Changes to the schematics upon Erik's advice.
Files for schematics revision
Schematics design review held. Needs major revision and prototyping of a simplified output stage.
Output stage simplified. Update of the schematics addressing the
points discussed in the revision
Files for Schematics Revision C
Schematics ready for layout. Contacting with Electronics Design Office.
Start of PCB layout.
Received BOM from DEM. Contacted with Cristine for components.
for using only one RTM motherboard for both conv-ttl-blo and conv-ttl-rs485 projects.
Rear Transition Module detection
PCB Review Agenda 20-01-2012
PCB Review Notes 20-01-2012
added. New wiki page:
on choosing replacements
for pulse transformers.
Waiting for OS-CON availability. Added
and schematics for
RTM Piggyback for Blocking
Schematics and PCB reviewed.
Improving schematics and PCB based on review.
Added more cores (control, multiboot and first image) to the project. See
HDL blocks status
Review Notes 20-02-2012](PCBN20022012-added)
3 prototypes ordered for 30-03-2012.
Prototypes received. Testing HDL simple repetition code.
DEM has not already soldered the RTM modules. One week to get them in the lab.
Basic repetition code works from SPI flash memory. Moving to PTS and ELMA interfacing.
WR core adapted to CONV-TTL-BLO. Bitstream has been generated. Pending the test of WR upon a set up of a WR link.
RTMs (CONV-TTL-BLO-RTM) received from DEM. Some issues found with the lenght of the pins in 100 pin connector.
A list of tests for CONV-TTL-BLO with the
Basic Functionality Bitstream
tests on image 1
. I2C HDL works and moving to SPI for m25p32 HDL core.
White Rabbit test core
A lot of work put on
. Reads and writes have been coarsed verified, still little details to give a final OK.
Speeding up for LS1.
Report of issues in CONV-TTL-BLO
Schematics design review of V2 held.
Report of the design review
up in repo.
ready for review.
Deployed a Blocking V1 in PS facilities. Source and bitstream available
Will build 4 V2's before building another 20 and after that 100. Ordered 25 RTM modules.
Received 4 V2 boards. Some assembly problems on two.
of the project to Thedi (Stana).
Order placed for 25
25x RTMs and 27x BLO-RTMPs received
Modifications needed for all three boards. Not expected before end of April.
Modifications complete for front module:
Modifications to RTMP done:
Modifications to RTM done:
25 CONV-TTL-BLO boards and front panels produced
10 rear panels produced
Ordered 30 ESD boxes for CONV-TTL-BLO boards
Received the ordered ESD boxes
Ordered 15 rear panels
Received 15 rear panels
Test system set up in LINAC 4 facility (see
page for more information)
Ordering 100 sets.
Design review held (see
Received 100 front module boards.
Added 100 front modules to stock.
Received 100 produced and assembled RTMs.
CONV-TTL-BLO now with diagnostics support.
Reviving the test system and studying
Prototype of blocking output stage built to verify proposed
Schematics, layout and front panel modification requests sent to DEM for V3
EDA-02446-V3-0 Ready for release. Order placed for 3 prototypes. Components ready
EDA-02446-V3-0 Three boards received. Outputs give unexpected overshoot. Will need a V4.
for v4 boards
v4 schematics, PCB layout, mechanical parts and manufacturing information available in
5 prototypes ordered of v4.0 boards, expected from 15-05-2017
5 v4 prototypes have been received, small error on silkscreen leads to issue #1611
Schematics v4-1 released on
to resolve issue #1611
Prototypes with new firmware successfully running on installations. Error-free since July 20th. Launch of large scale production. 460 motherboards and 405 RTM modules
pre-series of 25 v4.1 boards have been delivered to CERN
405 boards of CONV-TTL-RTM-BLO, EDA-02453 v3.2 delivered at CERN
Theodor-Adrian Stana, Carlos Gil-Soriano, Erik van der Bij, Denia Bouhired - August 23rd, 2018
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