Review06022012
CONV TTL BLOCKING schematics and PCB review 06-02-2012
Matthieu Cattin
conv-ttl-blo, conv-ttl-rtm, conv-ttl-rtm-blo schematics review
Schematics
conv-ttl-blo
- VME connector designator are P1 and P2, all other connectors are
Jx.
P1 and P2 should be put as a text comment next to the corresponding connector. - J12 should be marked as not mounted.
- IC11E should be either on FPGAps.SchDoc or PowerSupplyBlocking.SchDoc.
- Remove the comment about "OS-CON" on sheet PowerSupplyBlocking.SchDoc.
- Are the 2x 100ohms on FPGA_PROM_CCLK needed?
- FPGA_DONE pull-up is 100ohm, is that normal?
- MGTRREF with 2x 100ohm? Will it work?
- IC13 (PLL) powering different as on the SPEC!
- What does the comment "Separated clock lines for improving signal
integrity"
on sheet Clocks&Monitor.SchDoc mean? - I'd change comment "Thermometer will be used to have a FPGA unique ID" on sheet JTAG&Button.SchDoc
- "Extra switch" -> "RFU switches"
- I don't understand the comment (on sheet VME64xConn.SchDoc)
"SYSRESET_N can be used to trigger a FPGA reset from the control panel or issued remotely
by the monitor board. To reset only one board of the VME crate, it is necessary to set active
reception of SYSRESET_N pin of the board through I2C thanks to the VME64X geographical address." - MGTAVxx_123 pins are connected to GND. Is it the way to do?
- BOM: 10uF and 22uF!
conv-ttl-rtm
- Comment for layout engineer should be removed in the final version.
conv-ttl-rtm-blo
- Comment for layout engineer should be removed in the final version.
- Comment on TVS should be moved from Panel.SchDoc to RearChannel.SchDoc
- Should use the same LEDs as on the main board.
PCB
conv-ttl-blo
- Why are TOP, L3, L6 and BOTTOM filled with a GND polygon?
- Put more vias to connect the power planes to the source (BLO_24V, P3V3, P1V2).
- Add project URL on top silkscreen.
- Some vias doesn't have solder mask tenting.
- P1V2 plane is still tiny!
- Make PLO_24V plane rectangle.
- P3V3_IC7 plane could be rectangle.
- C110 (1uF) should be removed, 100nF should be place next to each GTP power pins!
- P3V3_VME can be connected with a polygon on top layer.
- Analogue DAC signal (PLLDAC_OUT1) still crossing the FPGA!
- All clocking stuff can be placed on the same side of the FPGA.
- As already said, the gigabit pairs could be routed on top (without changing layer 3 times)!
- I'd rather spread GND test points (B1->B6) all around the PCB.
- Solder mask expansion is 0mm.
front-panel
- GPx in not very informative. Shouldn't we put inverter or something like this?
- We could draw a box around WR LEDs.
arrangement
- What are those lines on the rear 3D view?