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CONV TTL BLOCKING schematics and PCB review 06-02-2012
Matthieu Cattin
conv-ttl-blo, conv-ttl-rtm, conv-ttl-rtm-blo schematics review
Schematics
conv-ttl-blo
- VME connector designator are P1 and P2, all other connectors are
Jx.
P1 and P2 should be put as a text comment next to the corresponding connector.- This refers to the way the VME64x component connector is specified in the CERNlib. It will be reported to DEM.
- J12 should be marked as not mounted.
- Change accepted.
- IC11E should be either on FPGAps.SchDoc or
PowerSupplyBlocking.SchDoc.
- Change accepted.
- Remove the comment about "OS-CON" on sheet
PowerSupplyBlocking.SchDoc.
- Change accepted.
- Are the 2x 100ohms on FPGA_PROM_CCLK needed?
- Yes they are. It is shown in Spartan document UG380 on page 52.
- FPGA_DONE pull-up is 100ohm, is that normal?
- Change accepted. Now are 4K7
- MGTRREF with 2x 100ohm? Will it work?
- The traces are properly matched by DEM. The via can be moved slightly closer.
- IC13 (PLL) powering different as on the SPEC!
- Change accepted.
- What does the comment "Separated clock lines for improving signal
integrity"
on sheet Clocks&Monitor.SchDoc mean?- Legacy comment. Now is deleted.
- I'd change comment "Thermometer will be used to have a FPGA unique
ID" on sheet JTAG&Button.SchDoc
- We can leave it.
- "Extra switch" -> "RFU switches"
- Change accepted.
- I don't understand the comment (on sheet VME64xConn.SchDoc)
"SYSRESET_N can be used to trigger a FPGA reset from the control panel or issued remotely
by the monitor board. To reset only one board of the VME crate, it is necessary to set active
reception of SYSRESET_N pin of the board through I2C thanks to the VME64X geographical address."- Functionality comment. Removed from schematics.
- MGTAVxx_123 pins are connected to GND. Is it the way to do?
- Yes it is. It is shown in Spartan document UG386 on page 123.
- BOM: 10uF and 22uF!
- Now everything is 22uF.
conv-ttl-rtm
- Comment for layout engineer should be removed in the final version.
- It has been decided that it is good to have layout tips in schematics.
conv-ttl-rtm-blo
- Comment for layout engineer should be removed in the final version.
- It has been decided that it is good to have layout tips in schematics.
- Comment on TVS should be moved from Panel.SchDoc to
RearChannel.SchDoc
- Change accepted
- Should use the same LEDs as on the main board.
- No. These LEDs are straight LEDs with board spacer, the others are L-shaped LEDs with board spacer.
PCB
conv-ttl-blo
- Why are TOP, L3, L6 and BOTTOM filled with a GND polygon?
- It should be removed as it produces islands.
- Put more vias to connect the power planes to the source (BLO_24V,
P3V3, P1V2).
- Change on hold: DEM recommends leaving vias as done now. It is able to transport enough current.
- Add project URL on top silkscreen.
- Change accepted.
- Some vias doesn't have solder mask tenting.
- DEM changed it.
- P1V2 plane is still tiny!
- Change accepted: DEM done it.
- Make BLO_24V plane rectangle.
- Change rejected. Not a good idea, as it will be close FPGA vias and there is already enough space.
- P3V3_IC7 plane could be rectangle.
- OK
- C110 (1uF) should be removed, 100nF should be place next to each GTP
power pins!
- Change rejected. It is correctly layouted.
- P3V3_VME can be connected with a polygon on top layer.
- Change accepted: we have more pins to get the current from on TOP.
- Analogue DAC signal (PLLDAC_OUT1) still crossing the FPGA!
- Important: Change accepted. It should not cross the FPGA.
- All clocking stuff can be placed on the same side of the FPGA.
- Important: Change accepted.
- As already said, the gigabit pairs could be routed on top (without
changing layer 3 times)!
- Change rejected.
- I'd rather spread GND test points (B1->B6) all around the PCB.
- OK
- Solder mask expansion is 0mm.
- Good point. Important.
front-panel
- GPx in not very informative. Shouldn't we put inverter or something
like this?
- Change accepted.
- We could draw a box around WR LEDs.
- Change accepted.
arrangement
- What are those lines on the rear 3D view?
-
Should be removed.
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-
Should be removed.