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C
Conv TTL RS485 - Gateware
Commit 03a4b568 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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WIP test bench

parent c1ebffb5
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Showing with 80 additions and 26 deletions
sim/print_pkg.vhd
View file @ 03a4b568
......@@ -135,6 +135,8 @@ PACKAGE print_pkg IS
PROCEDURE print_now_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_now_s_std (s: IN string; vec: IN std_logic_vector);
PROCEDURE print_now_s_std_s_std (s1: IN string; vec1: IN std_logic_vector;s2: IN string; vec2: IN std_logic_vector);
PROCEDURE print_now_s_std_s(s1: IN string; vec1: IN std_logic_vector;s2: IN string);
FUNCTION char_to_std_logic_vector(arg : character) RETURN std_logic_vector;
FUNCTION std_logic_vector_to_char(arg : std_logic_vector(7 DOWNTO 0)) RETURN character;
......@@ -633,6 +635,21 @@ PACKAGE BODY print_pkg IS
END print_now_s_std_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_now_s_std_s(s1: IN string; vec1: IN std_logic_vector;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s1);
HWRITE(l, vec1);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_std_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert character to std_logic_vector
FUNCTION char_to_std_logic_vector( arg : character) RETURN std_logic_vector IS
......
sim/testbench.vhd
View file @ 03a4b568
......@@ -68,18 +68,14 @@ architecture behav of testbench is
signal gf_en_n_in : std_logic;
signal ttl_n_in, ttl_out : std_logic_vector(C_NR_CHANS-1 downto 0);
signal rs485_n_in : std_logic_vector(C_NR_CHANS-1 downto 0);
signal ttl_n_in, ttl_out : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '0');
signal rs485_n_in, rs485_n_out : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '0');
-- signal sscl_in : std_logic;
-- signal ssda_in : std_logic;
signal sscl_out : std_logic;
signal sscl_en_out : std_logic;
signal ssda_out : std_logic;
signal ssda_en_out : std_logic;
-- signal mscl_in : std_logic;
-- signal msda_in : std_logic;
signal mscl_out : std_logic;
signal mscl_en_out : std_logic;
signal msda_out : std_logic;
......@@ -112,13 +108,13 @@ architecture behav of testbench is
signal adr : std_logic_vector(31 downto 0);
procedure read_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out: in t_i2c_master_out;
constant slv_addr : in std_logic_vector(6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
signal rcvd_val : out std_logic_vector(31 downto 0);
constant exp_val : in std_logic_vector(31 downto 0)) is
procedure read_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out: in t_i2c_master_out;
constant slv_addr : in std_logic_vector(6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
signal rcvd_val : out std_logic_vector(31 downto 0);
constant exp_val : in std_logic_vector(31 downto 0)) is
begin
print_now ("-------------------------------------------------");
print_now("read_i2c: start");
......@@ -143,12 +139,42 @@ architecture behav of testbench is
if i2c_m_out.i2c_master_rcvd_val = exp_val then
print_now_s_s("[OK] Correct reading from reg ", reg_name, "; expected value matches read value");
else
print_now_s_std_s_std("-------> [ERR]: Read value", i2c_master_rcvd_val,
print_now_s_std_s_std("-------> [ERR]: Read value ", i2c_master_rcvd_val,
" expected value ",exp_val);
end if;
print_now ("-------------------------------------------------");
end procedure read_i2c;
procedure write_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out : in t_i2c_master_out;
constant slv_addr : in std_logic_vector( 6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
constant send_val : in std_logic_vector(31 downto 0)) is
begin
print_now ("-------------------------------------------------");
print_now("write_i2c: start");
i2c_m_in.i2c_master_start <= '0';
i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
i2c_m_in.i2c_master_slv_addr <= "1011110";
i2c_m_in.i2c_master_reg_addr <= (others => '0');
i2c_m_in.i2c_master_send_val <= (others => '1');
wait for 1us;
i2c_m_in.i2c_master_slv_addr <= slv_addr;
i2c_m_in.i2c_master_reg_addr <= reg_addr;
i2c_m_in.i2c_master_send_val <= send_val;
i2c_m_in.i2c_master_start <= '1';
i2c_m_in.i2c_master_rdwr <= '0'; --0: write
wait for C_CLK_20_PER;
i2c_m_in.i2c_master_start <= '0';
wait until i2c_m_out.i2c_master_ready = '1';
print_now_s_std_s("write_i2C: Value ", send_val, " written to reg " & reg_name);
print_now ("-------------------------------------------------");
end procedure write_i2c;
--==============================================================================
-- architecture begin
--==============================================================================
......@@ -164,7 +190,6 @@ begin
clk_20_i => clk_20,
clk_125_p_i => clk_125_p,
clk_125_n_i => clk_125_n,
-- I2C interface
scl_i => scl,
scl_o => sscl_out,
......@@ -191,7 +216,7 @@ begin
-- Rear panel channels
rs485_n_i => rs485_n_in, --: in std_logic_vector(5 downto 0);
rs485_fs_n_i => (others => '0'), --: in std_logic_vector(5 downto 0); --failsafe?
rs485_o => open, --: out std_logic_vector(5 downto 0);
rs485_o => rs485_n_out, --: out std_logic_vector(5 downto 0);
-- Rear input and output termination lines
iterm_en_o => open,
oterm_en_o => open,
......@@ -353,10 +378,15 @@ begin
read_i2c (i2c_m_in, i2c_m_out, "1011110", c_REG_MAP(0).reg_addr, c_REG_MAP(0).reg_name, i2c_master_rcvd_val, C_BOARD_ID);
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- I2C writing of a big value to Front Panel Counter 1
write_i2c (i2c_m_in, i2c_m_out, "1011110", c_REG_MAP(4).reg_addr, c_REG_MAP(4).reg_name, x"FFFFFFF0");
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Sending pulses to Front Panel Channel 1
nb_pulses_to_send_slv := std_logic_vector(to_unsigned(nb_pulses_to_send, nb_pulses_to_send_slv'length));
print_now_s_i("Sending TTL front pulses to Channel 1: ", nb_pulses_to_send);
print_now_s_i("Sending TTL pulses to Front Panel Channel 1: ", nb_pulses_to_send);
generate_pulse (ttl_n_in(0), nb_pulses_to_send, 200ns, 200ns);
---------------------------------------------------------------------------
......@@ -365,19 +395,23 @@ begin
-- Reading from the I2C Front Panel regs; read only first 2 Channels to speed up testbench
while not(i = 3) loop
if i = 0 then
read_i2c (i2c_m_in, i2c_m_out, "1011110", c_REG_MAP(i+4).reg_addr, c_REG_MAP(i+4).reg_name , i2c_master_rcvd_val, nb_pulses_to_send_slv);
-- Front Panel Channel 1 register should roll over and read
read_i2c (i2c_m_in, i2c_m_out, "1011110", c_REG_MAP(i+4).reg_addr, c_REG_MAP(i+4).reg_name , i2c_master_rcvd_val, x"00000087");
else
-- Front Panel Channel 2 register should have not counted any pulses
read_i2c (i2c_m_in, i2c_m_out, "1011110", c_REG_MAP(i+4).reg_addr, c_REG_MAP(i+4).reg_name, i2c_master_rcvd_val, (others =>'0'));
end if;
i := i + 1;
end loop;
---------------------------------------------------------------------------
-- Reading from the I2C Rear Panel regs; read only first 2 Channels to speed up testbench
-- Reading from the I2C Rear Panel regs; read only first Channel to speed up testbench
i := 0;
while not(i = 3) loop
while not(i = 2) loop
if i = 0 then
-- Check Rear Panel Channel 1 counter has not counted any pulses
read_i2c (i2c_m_in, i2c_m_out, "1011110", c_REG_MAP(i+10).reg_addr, c_REG_MAP(i+10).reg_name , i2c_master_rcvd_val, (others =>'0'));
else
-- Check Rear Panel Channel 1 counter has not counted any pulses
read_i2c (i2c_m_in, i2c_m_out, "1011110", c_REG_MAP(i+10).reg_addr, c_REG_MAP(i+10).reg_name, i2c_master_rcvd_val, (others =>'0'));
end if;
i := i + 1;
......@@ -385,16 +419,19 @@ begin
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Sending 150 more pulses to Front Panel Channel 1, to make the counter roll
print_now_s_i("Sending TTL front pulses to Channel 1: ", nb_pulses_to_send);
generate_pulse (ttl_n_in(0), nb_pulses_to_send, 200ns, 200ns);
-- Sending 150 pulses to Rear Panel Channel 2
nb_pulses_to_send := 5;
print_now_s_i("Sending pulses to Rear Panel Channel 1: ", nb_pulses_to_send);
generate_pulse (rs485_n_in(1), nb_pulses_to_send, 200ns, 200ns);
---------------------------------------------------------------------------
-- Reading from the I2C Front Panel regs; read one reg read to speed up testbench
i := 0;
while not(i = 2) loop
-- Reading from the I2C Front Panel regs; read one reg to speed up testbench
i := 6;
while not(i = 8) loop
if i = 0 then
-- Check Rear Panel Channel 1 counter has correctly counted the pulses
read_i2c (i2c_m_in, i2c_m_out, "1011110", c_REG_MAP(i+4).reg_addr, c_REG_MAP(i+4).reg_name , i2c_master_rcvd_val, nb_pulses_to_send_slv);
else
-- Check Rear Panel Channel 2 has not counted any pulses
read_i2c (i2c_m_in, i2c_m_out, "1011110", c_REG_MAP(i+4).reg_addr, c_REG_MAP(i+4).reg_name, i2c_master_rcvd_val, (others =>'0'));
end if;
i := i + 1;
......
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