<propertyxil_pn:name="Implementation Top File"xil_pn:value="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"xil_pn:valueState="non-default"/>
<propertyxil_pn:name="Implementation Top Instance Path"xil_pn:value="/gc_frequency_meter"xil_pn:valueState="non-default"/>
>>>>>>> EG_sim
<propertyxil_pn:name="Include 'uselib Directive in Verilog File"xil_pn:value="false"xil_pn:valueState="default"/>
<propertyxil_pn:name="Include SIMPRIM Models in Verilog File"xil_pn:value="false"xil_pn:valueState="default"/>
<propertyxil_pn:name="Include UNISIM Models in Verilog File"xil_pn:value="false"xil_pn:valueState="default"/>
<propertyxil_pn:name="Include sdf_annotate task in Verilog File"xil_pn:value="true"xil_pn:valueState="default"/>