Commit 060e706b authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

SIM:Added simulation files

parent 8c161b87
This diff is collapsed.
Preliminary testebench specification
Connect I/O of conv-ttl-xxx board:
- Connect Chx front - Send n pulses
- Connect Chy rear - Send m pulses
- Connect inverter channel to a signal
- Connect RTM lines to pattern (Eg: conv-ttl-rs485-rtm-db9)
-------------------------------------------
* Check output ports:
- Check chx front AND rear outputs correspond to front-input
- Check chy front AND rear outputs correspond to rear-input
- Check output channel is exactly the inverted version of the input
-Check all LEDs blink correctly
-------------------------------------------
Implementing I2C master, scheck following:
*Check pulse counters"
- Check pulse counters show correct values for chx (front n pulses, rear 0)
and chy (front 0 pulses, rear m)
- Check counters roll-over when max value reached
- Check counters can be reset remotely
*Check switches:
- Activate "ttl-bar" mode
- Input ttl pulses on chx, check output is inverted
- Activate glitch filter
- Send pulse shorter than 50ns -> check pulse is ignored
- Send pulse longer than 50ns -> check output is synched to clock
* Check RTM line register is correct
* Check correct flagging of errors:
- I2C error (see manual)
* Check time stamping
- Check pulse timetag in last timestamp register
\ No newline at end of file
diff --git a/top/conv_common_gw.vhd b/top/conv_common_gw.vhd
index 489f311..504a661 100644
--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -57,6 +57,9 @@ use work.conv_common_gw_pkg.all;
entity conv_common_gw is
generic
(
+ -- Reduces some timeouts to speed up simulations
+ g_simul : boolean := false;
+
-- Number of repeater channels
g_nr_chans : integer := 6;
-- Number of inverter channels
@@ -314,6 +317,7 @@ architecture arch of conv_common_gw is
signal rst_20_n : std_logic;
signal rst_20 : std_logic;
signal rst_ext : std_logic;
+ signal rst_time : positive := 10;
-- Pulse logic signals
signal trig_a : std_logic_vector(g_nr_chans-1 downto 0);
@@ -543,12 +547,14 @@ begin
-- External reset input to reset generator
rst_ext <= rst_fr_reg or (not vme_sysreset_n_i);
+ -- Reset time: 50ns * 2 * (10**6) = 100 ms
+ rst_time <= 10; --2*(10**6) when g_simul = FALSE else 10;
+
-- Configure reset generator for 100ms reset
cmp_reset_gen : conv_reset_gen
generic map
(
- -- Reset time: 50ns * 2 * (10**6) = 100 ms
- g_reset_time => 2*(10**6)
+ g_reset_time => rst_time
)
port map
(
diff --git a/top/conv_common_gw_pkg.vhd b/top/conv_common_gw_pkg.vhd
index e8a0787..1271ca1 100644
--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd
@@ -71,6 +71,8 @@ package conv_common_gw_pkg is
component conv_common_gw is
generic
(
+ -- Reduces some timeouts to speed up simulations
+ g_simul : boolean := false;
-- Number of repeater channels
g_nr_chans : integer := 6;
g_nr_inv_chans : integer := 4;
diff --git a/ip_cores/conv-common-gw b/ip_cores/conv-common-gw
--- a/ip_cores/conv-common-gw
+++ b/ip_cores/conv-common-gw
@@ -1 +1 @@
-Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec
+Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec-dirty
diff --git a/top/conv_ttl_rs485.vhd b/top/conv_ttl_rs485.vhd
index 40adb75..53750f0 100644
--- a/top/conv_ttl_rs485.vhd
+++ b/top/conv_ttl_rs485.vhd
@@ -49,6 +49,7 @@ use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_ttl_rs485 is
+ generic (g_simul : boolean := FALSE);
port
(
-- Clocks
@@ -335,7 +336,7 @@ begin
cmp_conv_common : conv_common_gw
generic map
(
- -- Number of repeater channels
+ g_simul => g_simul,
g_nr_chans => c_nr_chans,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
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