Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
Conv TTL RS485 - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Conv TTL RS485 - Gateware
Commits
1351d6b2
Commit
1351d6b2
authored
Feb 19, 2018
by
Evangelia Gousiou
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
added test for timetag reg and test for INV channels
parent
9c4bd1d7
Expand all
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
140 additions
and
39 deletions
+140
-39
testbench.vhd
sim/testbench.vhd
+105
-37
testbench_pkg.vhd
sim/testbench_pkg.vhd
+35
-2
No files found.
sim/testbench.vhd
View file @
1351d6b2
This diff is collapsed.
Click to expand it.
sim/testbench_pkg.vhd
View file @
1351d6b2
...
@@ -50,6 +50,8 @@ package testbench_pkg is
...
@@ -50,6 +50,8 @@ package testbench_pkg is
constant
C_RTM
:
std_logic_vector
(
5
downto
0
)
:
=
"010101"
;
constant
C_RTM
:
std_logic_vector
(
5
downto
0
)
:
=
"010101"
;
constant
C_INITIAL_TST_VALUE
:
std_logic_vector
(
31
downto
0
)
:
=
x"FFFFFFF0"
;
constant
C_INITIAL_TST_VALUE
:
std_logic_vector
(
31
downto
0
)
:
=
x"FFFFFFF0"
;
constant
C_I2C_MASTER_SLV_ADDR
:
std_logic_vector
(
6
downto
0
)
:
=
"1011110"
;
-- DUT register map:
-- DUT register map:
constant
C_BIDR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
constant
C_BIDR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
...
@@ -72,6 +74,10 @@ package testbench_pkg is
...
@@ -72,6 +74,10 @@ package testbench_pkg is
constant
C_CH5RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000038"
;
constant
C_CH5RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000038"
;
constant
C_CH6RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000003C"
;
constant
C_CH6RPPCR
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000003C"
;
constant
CH1LTSCYR
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000005C"
;
constant
CH1LTSTLR
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000060"
;
type
t_reg
is
type
t_reg
is
record
record
reg_addr
:
std_logic_vector
(
31
downto
0
);
reg_addr
:
std_logic_vector
(
31
downto
0
);
...
@@ -279,6 +285,9 @@ end component conv_ttl_rs485;
...
@@ -279,6 +285,9 @@ end component conv_ttl_rs485;
constant
exp_val
:
in
std_logic_vector
(
31
downto
0
);
constant
exp_val
:
in
std_logic_vector
(
31
downto
0
);
err
:
out
natural
);
err
:
out
natural
);
procedure
read_i2c_err
(
signal
i2c_m_in
:
out
t_i2c_master_in
;
signal
i2c_m_out
:
in
t_i2c_master_out
);
end
testbench_pkg
;
end
testbench_pkg
;
package
body
testbench_pkg
is
package
body
testbench_pkg
is
--==================================================================================================
--==================================================================================================
...
@@ -388,7 +397,7 @@ package body testbench_pkg is
...
@@ -388,7 +397,7 @@ package body testbench_pkg is
print_now
(
"read_i2c: start"
);
print_now
(
"read_i2c: start"
);
i2c_m_in
.
i2c_master_start
<=
'0'
;
i2c_m_in
.
i2c_master_start
<=
'0'
;
i2c_m_in
.
i2c_master_rdwr
<=
'0'
;
--mst_fsm_op
i2c_m_in
.
i2c_master_rdwr
<=
'0'
;
--mst_fsm_op
i2c_m_in
.
i2c_master_slv_addr
<=
"1011110"
;
i2c_m_in
.
i2c_master_slv_addr
<=
C_I2C_MASTER_SLV_ADDR
;
i2c_m_in
.
i2c_master_reg_addr
<=
(
others
=>
'0'
);
i2c_m_in
.
i2c_master_reg_addr
<=
(
others
=>
'0'
);
i2c_m_in
.
i2c_master_send_val
<=
(
others
=>
'1'
);
i2c_m_in
.
i2c_master_send_val
<=
(
others
=>
'1'
);
wait
for
1
us
;
wait
for
1
us
;
...
@@ -429,7 +438,7 @@ package body testbench_pkg is
...
@@ -429,7 +438,7 @@ package body testbench_pkg is
print_now
(
"write_i2c: start"
);
print_now
(
"write_i2c: start"
);
i2c_m_in
.
i2c_master_start
<=
'0'
;
i2c_m_in
.
i2c_master_start
<=
'0'
;
i2c_m_in
.
i2c_master_rdwr
<=
'0'
;
--mst_fsm_op
i2c_m_in
.
i2c_master_rdwr
<=
'0'
;
--mst_fsm_op
i2c_m_in
.
i2c_master_slv_addr
<=
"1011110"
;
i2c_m_in
.
i2c_master_slv_addr
<=
C_I2C_MASTER_SLV_ADDR
;
i2c_m_in
.
i2c_master_reg_addr
<=
(
others
=>
'0'
);
i2c_m_in
.
i2c_master_reg_addr
<=
(
others
=>
'0'
);
i2c_m_in
.
i2c_master_send_val
<=
(
others
=>
'1'
);
i2c_m_in
.
i2c_master_send_val
<=
(
others
=>
'1'
);
wait
for
1
us
;
wait
for
1
us
;
...
@@ -448,6 +457,30 @@ package body testbench_pkg is
...
@@ -448,6 +457,30 @@ package body testbench_pkg is
end
procedure
write_i2c
;
end
procedure
write_i2c
;
----------------------------------------------------------------------------------------------------
procedure
read_i2c_err
(
signal
i2c_m_in
:
out
t_i2c_master_in
;
signal
i2c_m_out
:
in
t_i2c_master_out
)
is
variable
err_cnt
:
natural
:
=
0
;
begin
print_now
(
"---------------"
);
print_now
(
"read_i2c_err: start"
);
i2c_m_in
.
i2c_master_start
<=
'0'
;
i2c_m_in
.
i2c_master_rdwr
<=
'0'
;
--mst_fsm_op
i2c_m_in
.
i2c_master_slv_addr
<=
"1011111"
;
i2c_m_in
.
i2c_master_reg_addr
<=
(
others
=>
'0'
);
i2c_m_in
.
i2c_master_send_val
<=
(
others
=>
'1'
);
wait
for
1
us
;
i2c_m_in
.
i2c_master_slv_addr
<=
"1011111"
;
i2c_m_in
.
i2c_master_reg_addr
<=
x"F1F1F1F1"
;
i2c_m_in
.
i2c_master_start
<=
'1'
;
i2c_m_in
.
i2c_master_rdwr
<=
'1'
;
--read
wait
for
C_CLK_20_PER
;
i2c_m_in
.
i2c_master_start
<=
'0'
;
wait
until
i2c_m_out
.
i2c_master_ready
=
'1'
;
print_now
(
"---------------"
);
end
procedure
read_i2c_err
;
end
;
end
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment