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Conv TTL RS485 - Gateware
Commit 1e5e7608 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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updated modelsim .do; updated .xise project to include simulation

parent 7d1e1f2c
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sim/run.do
View file @ 1e5e7608
#
# Create work library
#
vlib work
vsim -t 1 ms -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
#add wave *
do wave.do
run 1 ms
wave zoomfull
#
# Compile sources
#
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/fastevent_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
vcom -explicit -93 "./print_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
vcom -explicit -93 "../top/conv_ttl_rs485.vhd"
vcom -explicit -93 "./testbench_pkg.vhd"
vcom -explicit -93 "./i2c_master_and_driver.vhd"
vcom -explicit -93 "./i2c_bus_model.vhd"
vcom -explicit -93 "./testbench.vhd"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ns -lib work work.testbench
#
# Source the wave do file
#
do {testbench_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {testbench.udo}
#
# Run simulation for this time
#
run 2 ms
#
# End
#
\ No newline at end of file
sim/tb_run.do 0 → 100644
View file @ 1e5e7608
#
# Create work library
#
vlib work
#
# Compile sources
#
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/fastevent_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
vcom -explicit -93 "./print_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
vcom -explicit -93 "../top/conv_ttl_rs485.vhd"
vcom -explicit -93 "./testbench_pkg.vhd"
vcom -explicit -93 "./i2c_master_and_driver.vhd"
vcom -explicit -93 "./i2c_bus_model.vhd"
vcom -explicit -93 "./testbench.vhd"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ns -lib work work.testbench
#
# Source the wave do file
#
do {testbench_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {testbench.udo}
#
# Run simulation for this time
#
run 2 ms
#
# End
#
\ No newline at end of file
syn/Release/conv_ttl_rs485.xise
View file @ 1e5e7608
......@@ -68,6 +68,7 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Do File Behavioral" xil_pn:value="../../sim/tb_run.do" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
......@@ -293,7 +294,7 @@
<property xil_pn:name="Simulation Resolution" xil_pn:value="100 ps" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="20000 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
......
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