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Conv TTL RS485 - Gateware
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Conv TTL RS485 - Gateware
Commits
4d40bcc3
Commit
4d40bcc3
authored
Oct 17, 2017
by
Denia Bouhired-Ferrag
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style fixes, removed commented-out, old LED process
parent
11f6c953
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45 deletions
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-45
conv_ttl_rs485.vhd
top/conv_ttl_rs485.vhd
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top/conv_ttl_rs485.vhd
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4d40bcc3
...
...
@@ -249,6 +249,7 @@ begin
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
p_ttlbar_nosig
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
...
...
@@ -274,14 +275,16 @@ begin
-- Pulse input on RS-485 side valid only when failsafe not high
-- see Texas slyt257 for implementation details
gen_rs485_input
:
for
i
in
0
to
c_nr_chans
-1
generate
rs485_fs
(
i
)
<=
rs485_n_i
(
i
)
nor
rs485_fs_n_i
(
i
);
pulse_rs485
(
i
)
<=
(
not
rs485_n_i
(
i
))
when
rs485_fs
(
i
)
=
'0'
else
'0'
;
pulse_rs485
(
i
)
<=
(
not
rs485_n_i
(
i
))
when
rs485_fs
(
i
)
=
'0'
else
'0'
;
end
generate
gen_rs485_input
;
-- This process has the effect of extending the reset an extra 100 us, to avoid
-- a pulse being generated or erroneously counted during the period of no signal
-- detect
p_inhibit_first_pulse
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
...
...
@@ -299,6 +302,7 @@ begin
-- Delay inhibit first pulse signal, use this to enable input, thus avoiding
-- internal reset states of conv_common_gw
p_inhibit_first_pulse_d0
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
...
...
@@ -311,8 +315,9 @@ begin
end
process
;
-- Pulse input valid only after inhibit period is over
pulse_in
<=
(
pulse_ttl
or
pulse_rs485
)
when
(
inhibit_first_pulse_d0
=
'0'
)
else
(
others
=>
'0'
);
pulse_in
<=
(
pulse_ttl
or
pulse_rs485
)
when
(
inhibit_first_pulse_d0
=
'0'
)
else
(
others
=>
'0'
);
-- Line inputs for reflection in status register
line_ttl
<=
not
ttl_n_i
;
...
...
@@ -472,15 +477,16 @@ begin
ttl_o
<=
pulse_out
when
sw_ttl
=
'1'
else
not
pulse_out
;
rs485_o
(
1
downto
0
)
<=
pulse_out
(
1
downto
0
);
-- Channels 3 and 4 output copies of chans 1 and 2 respectively
-- depending on RTMP Id of RTM connected.
-- *RTM with DB9 connectors has only 2 o/p channels in rs485 RTMP = Gnd Open Gnd
-- *Optical RTM only 2 o/p channels in optical RTMP= Open Open Gnd
-- in these cases channel 3 copies channel 1
-- channel 4 copies channel 2
--
rs485_o
(
3
downto
2
)
<=
pulse_out
(
1
downto
0
)
when
rtmp_i
=
"101"
or
rtmp_i
=
"100"
else
pulse_out
(
3
downto
2
);
else
pulse_out
(
3
downto
2
);
rs485_o
(
5
downto
4
)
<=
pulse_out
(
5
downto
4
);
-- LED outputs
...
...
@@ -506,45 +512,6 @@ begin
iterm_en_o
<=
(
others
=>
sw_iterm_en
);
oterm_en_o
<=
(
others
=>
sw_oterm_en
);
-- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input
-- LED flash length: 26 ms
-- gen_inv_ttl_leds : for i in 0 to 3 generate
-- inv_n(i) <= inv_n_i(i);
-- p_pulse_led : process (clk_20_i) is
-- begin
-- if rising_edge(clk_20_i) then
-- if (rst_20_n = '0') then
-- inv_n_d0(i) <= '0';
-- inv_n_fedge_p(i) <= '0';
-- led_inv_cnt(i) <= (others => '0');
-- led_inv(i) <= '0';
-- else
-- inv_n_d0(i) <= inv_n(i);
-- inv_n_fedge_p(i) <= (not inv_n(i)) and inv_n_d0(i);
-- case led_inv(i) is
-- when '0' =>
-- if (inv_n_fedge_p(i) = '1') then
-- led_inv(i) <= '1';
-- end if;
-- when '1' =>
-- led_inv_cnt(i) <= led_inv_cnt(i) + 1;
-- if (led_inv_cnt(i) = (led_inv_cnt(i)'range => '1')) then
-- led_inv(i) <= '0';
-- end if;
-- when others =>
-- led_inv(i) <= '0';
-- end case;
-- end if;
-- end if;
-- end process p_pulse_led;
-- end generate gen_inv_ttl_leds;
-- LED outputs
-- led_front_o <= led_pulse;
-- led_inv_o <= led_inv;
-- led_rear_n_o <= not led_pulse;
--============================================================================
-- External logic for bicolor LED control
...
...
@@ -605,6 +572,7 @@ begin
bicolor_led_state
(
23
downto
22
)
<=
c_LED_OFF
;
end
architecture
arch
;
--==============================================================================
-- architecture end
--==============================================================================
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