Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
Conv TTL RS485 - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Conv TTL RS485 - Gateware
Commits
5f388fea
Commit
5f388fea
authored
Jan 27, 2015
by
Theodor-Adrian Stana
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
doc: Updated HDL guide to v1.1
parent
11bb7282
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
15 additions
and
2 deletions
+15
-2
cern-title.tex
doc/hdlg/cern-title.tex
+3
-1
hdlg-conv-ttl-rs485.tex
doc/hdlg/hdlg-conv-ttl-rs485.tex
+12
-1
No files found.
doc/hdlg/cern-title.tex
View file @
5f388fea
...
...
@@ -9,7 +9,9 @@
\noindent
\rule
{
\textwidth
}{
.1cm
}
\hfill
January 6, 2015
\hfill
Gateware v1.0
\hfill
January 27, 2015
\vspace*
{
3cm
}
...
...
doc/hdlg/hdlg-conv-ttl-rs485.tex
View file @
5f388fea
...
...
@@ -77,6 +77,7 @@ work, see \\
06-08-2014
&
0.1
&
First draft
\\
06-01-2015
&
0.2
&
Release for gateware v0.0
\\
06-01-2015
&
1.0
&
Updated memory map for gateware v1.0
\\
27-01-2015
&
1.1
&
Added repository download commands to Section~
\ref
{
sec:intro
}
\\
\hline
\end{tabular}
}
...
...
@@ -117,6 +118,16 @@ as a subproject and adds some external logic to it to adapt for peculiarities on
This document explains these peculiarities and the corresponding logic implemented, and lists
the memory map for the gateware in Appendix~
\ref
{
app:memmap
}
.
The HDL files can be obtained by cloning the repository along with its submodules using the following commands:
\begin{footnotesize}
\begin{verbatim}
git clone git://ohwr.org/level-conversion/conv-ttl-rs485/conv-ttl-rs485-gw.git
cd conv-ttl-rs485-gw/
git submodule update --init --recursive
\end{verbatim}
\end{footnotesize}
\subsection
{
Additional documentation
}
\begin{itemize}
...
...
@@ -137,7 +148,7 @@ will detail each of the blocks in the following sections. For a more
general look at the pulse repetition logic, refer to the CONV-TTL-RS485 User Guide~
\cite
{
conv-ttl-rs485-ug
}
.
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=1.
1
\textwidth]
{
fig/block-diagram
}}
\centerline
{
\includegraphics
[width=1.
08
\textwidth]
{
fig/block-diagram
}}
\caption
{
\label
{
fig:block-diagram
}
Block diagram of CONV-TTL-RS485 gateware
}
\end{figure}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment