Commit 771ca3df authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

WIP Merging with simulation branch

parents e18f593d 198e95b5
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C bus model
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-27
--
-- version: 1.0
--
-- description:
-- A very simple I2C bus model for use in simulation, implementing the
-- wired-AND on the I2C protocol.
--
-- Masters and slaves should implement the buffers internally and connect the
-- SCL and SDA lines to the input ports of this model, as below:
-- - masters should connect to mscl_i and msda_i
-- - slaves should connect to sscl_i and ssda_i
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-27 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end entity i2c_bus_model;
architecture behav of i2c_bus_model is
--==============================================================================
-- architecture begin
--==============================================================================
begin
scl_o <= '1' when (mscl_i = (mscl_i'range => '1')) and
(sscl_i = (sscl_i'range => '1')) else
'0';
sda_o <= '1' when (msda_i = (msda_i'range => '1')) and
(ssda_i = (ssda_i'range => '1')) else
'0';
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- I2C master and its driver
-- https://www.ohwr.org/projects/conv-common-gw
--------------------------------------------------------------------------------
--
-- unit name: Top-level simulation of conv_common_gw
--
-- description:
--
--
--
--------------------------------------------------------------------------------
-- Copyright (c) 2010-2012 CERN / BE-CO-HT
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity i2c_master_and_driver is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Driver interface
ready_o : out std_logic;
start_i : in std_logic;
finish_o : out std_logic;
rdwr_i : in std_logic; -- 1: read, 0: write
slv_addr_i : in std_logic_vector(6 downto 0);
reg_addr_i : in std_logic_vector(31 downto 0);
send_val_i : in std_logic_vector(31 downto 0);
rcvd_val_o : out std_logic_vector(31 downto 0);
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_oen : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oen : out std_logic
);
end entity i2c_master_and_driver;
architecture arch of i2c_master_and_driver is
type t_state_i2c_mst is
(
IDLE,
I2C_ADDR, I2C_ADDR_ACK,
WB_ADDR_B0, WB_ADDR_B0_ACK,
WB_ADDR_B1, WB_ADDR_B1_ACK,
ST_OP,
RD_RESTART, RD_RESTART_ACK,
RD, RD_ACK,
WR, WR_ACK,
STO,
SUCCESS,
ERR
);
-- I2C signals
signal state_i2c_mst : t_state_i2c_mst;
signal mst_sta : std_logic;
signal mst_sto : std_logic;
signal mst_rd : std_logic;
signal mst_wr : std_logic;
signal mst_ack : std_logic;
signal mst_dat_in : std_logic_vector(7 downto 0);
signal mst_dat_out : std_logic_vector(7 downto 0);
signal mst_cmd_ack : std_logic;
signal ack_fr_slv : std_logic;
signal cnt : unsigned(2 downto 0);
signal once : boolean;
signal byte_cnt : unsigned(1 downto 0);
signal rcvd : std_logic_vector(31 downto 0);
signal send : std_logic_vector(31 downto 0);
signal rst : std_logic;
begin
rst <= not rst_n_i;
-- from general-cores/modules/wishbone/wb_i2c_master/
cmp_master : entity work.i2c_master_byte_ctrl
port map(
clk => clk_i,
rst => rst,
nReset => rst_n_i,
ena => '1',
clk_cnt => x"0005", -------------x"0027",
-- input signals
start => mst_sta,
stop => mst_sto,
read => mst_rd,
write => mst_wr,
ack_in => mst_ack,
din => mst_dat_in,
-- output signals
cmd_ack => mst_cmd_ack,
ack_out => ack_fr_slv,
i2c_busy => open,
i2c_al => open,
dout => mst_dat_out,
-- i2c lines
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
------------------------------------------------------------------------------
-- This FSM controls the signals to the master component to implement the I2C
-- protocol defined together with ELMA. The FSM is controlled by the
-- stimuli process below
------------------------------------------------------------------------------
p_mst_fsm : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state_i2c_mst <= IDLE;
mst_sta <= '0';
mst_wr <= '0';
mst_sto <= '0';
mst_rd <= '0';
mst_dat_in <= (others => '0');
mst_ack <= '0';
cnt <= (others => '0');
once <= true;
byte_cnt <= (others => '0');
rcvd <= (others => '0');
send <= (others => '0');
ready_o <= '0';
finish_o <= '0';
else
case state_i2c_mst is
when IDLE =>
if (start_i = '1') then
state_i2c_mst <= I2C_ADDR;
send <= std_logic_vector(send_val_i);
ready_o <= '0';
else
ready_o <= '1';
end if;
finish_o <= '0';
when I2C_ADDR =>
mst_sta <= '1';
mst_wr <= '1';
mst_dat_in <= slv_addr_i & '0';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= I2C_ADDR_ACK;
end if;
when I2C_ADDR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B0;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B0 =>
mst_wr <= '1';
mst_dat_in <= reg_addr_i(15 downto 8);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B0_ACK;
end if;
when WB_ADDR_B0_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B1;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B1 =>
mst_wr <= '1';
mst_dat_in <= reg_addr_i(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B1_ACK;
end if;
when WB_ADDR_B1_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= ST_OP;
else
state_i2c_mst <= ERR;
end if;
end if;
when ST_OP =>
if (rdwr_i = '1') then
state_i2c_mst <= RD_RESTART;
else
state_i2c_mst <= WR;
end if;
when RD_RESTART =>
mst_wr <= '1';
mst_dat_in <= slv_addr_i & '1';
mst_sta <= '1';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= RD_RESTART_ACK;
end if;
when RD_RESTART_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= RD;
rcvd <= (others => '0');
else
state_i2c_mst <= ERR;
end if;
end if;
when RD =>
mst_rd <= '1';
mst_ack <= '0';
if (byte_cnt = 3) then
mst_ack <= '1';
end if;
if (mst_cmd_ack = '1') then
mst_rd <= '0';
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when RD_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when WR =>
mst_wr <= '1';
mst_dat_in <= send(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WR_ACK;
end if;
when WR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
byte_cnt <= byte_cnt + 1;
send <= x"00" & send(31 downto 8);
state_i2c_mst <= WR;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
else
state_i2c_mst <= ERR;
end if;
end if;
when STO =>
mst_sto <= '1';
if (mst_cmd_ack = '1') then
mst_sto <= '0';
state_i2c_mst <= IDLE;
end if;
finish_o <= '1';
when ERR =>
if (once) then
report("Error!");
once <= false;
end if;
when others =>
state_i2c_mst <= ERR;
end case;
end if;
end if;
end process p_mst_fsm;
rcvd_val_o <= rcvd;
end architecture arch;
---------------------------------------------------------------
-- Title : Print Package
-- Project : none
---------------------------------------------------------------
-- File : print_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 26/08/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
-- several procedures and functions for screen printing
---------------------------------------------------------------
-- Hierarchy:
--
-- none
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.9 $
--
-- $Log: print_pkg.vhd,v $
-- Revision 1.9 2015/11/12 14:57:26 AGeissler
-- R1: Missing now procedure with one string
-- M1: Overload existing print_now_s with sting instead of integer
--
-- Revision 1.8 2015/11/12 13:56:46 AGeissler
-- R1: Missing character to std_logic_vector conversion function
-- M1: Added functions std_logic_vector_to_char and char_to_std_logic_vector
-- R2: Missing now procedures
-- M2: Added for each procedure a equivalent one, with an additional time print
--
-- Revision 1.7 2015/11/12 11:04:50 AGeissler
-- R1: The user shall decide, when and if spaces are used
-- M1: Removed spaces from print procedures
--
-- Revision 1.6 2015/03/10 10:20:34 AGeissler
-- R1: Improvement
-- M1.1: Added overloaded function for print_s_hb, print_s_hw, print_s_hl with std_logic_vector as parameter
-- M1.2: Replaced print_s_bit with print_s_std as a overloaded function with a std_logic as parameter
-- M1.3: Added short description for each function
--
-- Revision 1.5 2015/03/10 09:25:56 AGeissler
-- R1: Missing function to print an single bit
-- M1: Added function print_s_bit
--
-- Revision 1.4 2014/12/02 17:27:10 AGeissler
-- R1: Missing print functions for integer in hex with different sizes
-- M1: Added print functions print_s_hb, print_s_hw, print_s_hl
--
-- Revision 1.3 2014/11/24 11:26:00 AGeissler
-- R1: Missing function to print two strings for example text + time
-- (print_s(" it took ", time'image(tmp_time));)
-- M1: Added procedure print_s
--
-- Revision 1.2 2006/03/01 09:34:09 mmiehling
-- added print_now_s
--
-- Revision 1.1 2005/10/20 10:42:26 mmiehling
-- Initial Revision
--
-- Revision 1.1 2005/09/15 12:05:59 MMiehling
-- Initial Revision
--
-- Revision 1.2 2004/05/13 14:22:49 MMiehling
-- multifunction device support
--
-- Revision 1.1 2004/04/14 09:42:28 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_textio.all;
USE ieee.numeric_std.all;
LIBRARY std;
USE std.textio.all;
PACKAGE print_pkg IS
PROCEDURE print_mtest ( source : string;
address : std_logic_vector;
is_data : std_logic_vector;
should_data : std_logic_vector;
arg : boolean);
PROCEDURE print (s: IN string);
PROCEDURE print_s (s: IN string; s2: IN string);
PROCEDURE print_s_s (s: IN string; s2: IN string; s3: IN string);
PROCEDURE print_s_i (s: IN string; s2: IN integer);
PROCEDURE print_s_h (s: IN string; s2: IN integer);
PROCEDURE print_s_hb (s: IN string; s2: IN integer);
PROCEDURE print_s_hw (s: IN string; s2: IN integer);
PROCEDURE print_s_hl (s: IN string; s2: IN integer);
PROCEDURE print_s_hb (s: IN string; s2: IN std_logic_vector(7 DOWNTO 0));
PROCEDURE print_s_hw (s: IN string; s2: IN std_logic_vector(15 DOWNTO 0));
PROCEDURE print_s_hl (s: IN string; s2: IN std_logic_vector(31 DOWNTO 0));
PROCEDURE print_s_dl (s: IN string; s2: IN std_logic_vector);
PROCEDURE print_cycle ( header : string;
address : std_logic_vector;
data : std_logic_vector;
sel_o_int : std_logic_vector(3 DOWNTO 0);
ende : string);
PROCEDURE print_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_s_std (s: IN string; vec: IN std_logic_vector);
PROCEDURE print_time (s: IN string);
PROCEDURE print_sum (intext: IN string; mstr_err: IN integer; wb_err: IN integer);
-- now procedures
PROCEDURE print_now (s: IN string);
PROCEDURE print_now_s (s: IN string; s2: IN integer);
PROCEDURE print_now_s (s: IN string; s2: IN string);
PROCEDURE print_now_s_s (s: IN string; s2: IN string; s3: IN string);
PROCEDURE print_now_s_i (s: IN string; s2: IN integer);
PROCEDURE print_now_s_h (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hb (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hw (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hl (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hb (s: IN string; s2: IN std_logic_vector(7 DOWNTO 0));
PROCEDURE print_now_s_hw (s: IN string; s2: IN std_logic_vector(15 DOWNTO 0));
PROCEDURE print_now_s_hl (s: IN string; s2: IN std_logic_vector(31 DOWNTO 0));
PROCEDURE print_now_s_dl (s: IN string; s2: IN std_logic_vector);
PROCEDURE print_now_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_now_s_std (s: IN string; vec: IN std_logic_vector);
PROCEDURE print_now_s_std_s_std (s1: IN string; vec1: IN std_logic_vector;s2: IN string; vec2: IN std_logic_vector);
PROCEDURE print_now_s_std_s(s1: IN string; vec1: IN std_logic_vector;s2: IN string);
FUNCTION char_to_std_logic_vector(arg : character) RETURN std_logic_vector;
FUNCTION std_logic_vector_to_char(arg : std_logic_vector(7 DOWNTO 0)) RETURN character;
END print_pkg;
PACKAGE BODY print_pkg IS
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string with the current simulation time
PROCEDURE print_time(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITELINE(output,l);
END print_time;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic
PROCEDURE print_s_std(s: IN string; bit: IN std_logic) IS
VARIABLE l: line;
VARIABLE s2: string(1 TO 3);
BEGIN
WRITE(l, s);
IF bit = '1' THEN
s2 := "'1'";
ELSE
s2 := "'0'";
END IF;
WRITE(l, s2);
WRITELINE(output,l);
END print_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_s_std(s: IN string; vec: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, vec);
WRITELINE(output,l);
END print_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print wishbone information
PROCEDURE print_cycle( header : string;
address : std_logic_vector;
data : std_logic_vector;
sel_o_int: std_logic_vector(3 DOWNTO 0);
ende : string) IS
VARIABLE l : line;
BEGIN
WRITE(l,header);
WRITE(l,string'(" "));
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l,string'(" ADR: "));
HWRITE(l,address,justified=>left);
WRITE(l,string'(" DATA: "));
IF address(1) = '0' THEN
CASE sel_o_int IS
WHEN "1111" => HWRITE(l,data);
WHEN "0001" => HWRITE(l,data(7 DOWNTO 0));
WRITE(l,string'(" "));
WHEN "0010" => HWRITE(l,data(15 DOWNTO 8));
WRITE(l,string'(" "));
WHEN "0100" => HWRITE(l,data(23 DOWNTO 16));
WRITE(l,string'(" "));
WHEN "1000" => HWRITE(l,data(31 DOWNTO 24));
WRITE(l,string'(" "));
WHEN "0011" => HWRITE(l,data(15 DOWNTO 0));
WRITE(l,string'(" "));
WHEN "1100" => HWRITE(l,data(31 DOWNTO 16));
WRITE(l,string'(" "));
WHEN OTHERS => ASSERT FALSE REPORT "PRINT_PKG Error: sel_o is undefined" SEVERITY error;
END CASE;
ELSE
HWRITE(l,data);
END IF;
WRITE(l,string'(" "));
WRITE(l,ende);
WRITELINE(output,l);
END print_cycle;
----------------------------------------------------------------------------------------------------------------------------------------
-- print the result of a memory test
PROCEDURE print_mtest( source : string;
address : std_logic_vector;
is_data : std_logic_vector;
should_data : std_logic_vector;
arg : boolean) IS
VARIABLE tranx : line;
BEGIN
WRITE(tranx,source);
WRITE(tranx,now, justified=>right,field =>10, unit=> ns );
WRITE(tranx,string'(" Memory Test "));
WRITE(tranx,string'(" ADR: "));
HWRITE(tranx,address,justified=>left);
IF NOT arg THEN
WRITE(tranx,string'(" DATA should be: "));
HWRITE(tranx,should_data);
WRITE(tranx, string'(" is "));
ELSE
WRITE(tranx,string'(" DATA: "));
END IF;
HWRITE(tranx,is_data);
WRITE(tranx,string'(" "));
IF arg THEN
WRITE(tranx,string'("OK"));
ELSE
WRITE(tranx,string'("ERROR!"));
END IF;
WRITELINE(output,tranx);
END print_mtest;
----------------------------------------------------------------------------------------------------------------------------------------
-- print string
PROCEDURE print(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITELINE(output,l);
END print;
----------------------------------------------------------------------------------------------------------------------------------------
-- print two strings (for example to print string and time = print_s(" it took ", time'image(tmp_time));
PROCEDURE print_s(s: IN string;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print three strings (for example to print string, value and type = print_s(" it took ", integer, "ns");
PROCEDURE print_s_s(s: IN string; s2: IN string; s3: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITE(l, s3);
WRITELINE(output,l);
END print_s_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a integer as a decimal number
PROCEDURE print_s_i(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_s_i;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits (equal to print_s_hl but is needed to be backward compatible)
PROCEDURE print_s_h(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_s_h;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 2 digits
PROCEDURE print_s_hb(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,8)));
WRITELINE(output,l);
END print_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 4 digits
PROCEDURE print_s_hw(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,16)));
WRITELINE(output,l);
END print_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits
PROCEDURE print_s_hl(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 2 digits
PROCEDURE print_s_hb(s: IN string;s2: IN std_logic_vector(7 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 4 digits
PROCEDURE print_s_hw(s: IN string;s2: IN std_logic_vector(15 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 8 digits
PROCEDURE print_s_hl(s: IN string;s2: IN std_logic_vector(31 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a decimal number
PROCEDURE print_s_dl(s: IN string;s2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, to_integer(unsigned(s2)));
WRITELINE(output,l);
END print_s_dl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print the result of a test case
PROCEDURE print_sum(intext: IN string; mstr_err: IN integer; wb_err: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, string'(" "));
WRITELINE(output,l);
IF mstr_err = 0 AND wb_err = 0 THEN
WRITE(l, string'(" P A S S "));
WRITE(l, intext);
WRITELINE(output,l);
ELSE
WRITE(l, string'(" F A I L "));
WRITE(l, intext);
WRITELINE(output,l);
WRITE(l, string'(" Number of PCI errors: "));
WRITE(l, mstr_err);
WRITELINE(output,l);
WRITE(l, string'(" Number of WB errors: "));
WRITE(l, wb_err);
WRITELINE(output,l);
END IF;
WRITE(l, string'("*************************************************************************************************************"));
WRITELINE(output,l);
END print_sum;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string with the current simulation time
PROCEDURE print_now(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITELINE(output,l);
END print_now;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and an integer as decimal number withthe current simulation time
PROCEDURE print_now_s(s: IN string; s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print two strings (for example to print string and time = print_s(" it took ", time'image(tmp_time));
PROCEDURE print_now_s(s: IN string;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print three strings (for example to print string, value and type = print_s(" it took ", integer, "ns");
PROCEDURE print_now_s_s(s: IN string; s2: IN string; s3: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITE(l, s3);
WRITELINE(output,l);
END print_now_s_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a integer as a decimal number
PROCEDURE print_now_s_i(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_i;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits (equal to print_s_hl but is needed to be backward compatible)
PROCEDURE print_now_s_h(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_now_s_h;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 2 digits
PROCEDURE print_now_s_hb(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,8)));
WRITELINE(output,l);
END print_now_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 4 digits
PROCEDURE print_now_s_hw(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,16)));
WRITELINE(output,l);
END print_now_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits
PROCEDURE print_now_s_hl(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_now_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 2 digits
PROCEDURE print_now_s_hb(s: IN string;s2: IN std_logic_vector(7 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 4 digits
PROCEDURE print_now_s_hw(s: IN string;s2: IN std_logic_vector(15 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 8 digits
PROCEDURE print_now_s_hl(s: IN string;s2: IN std_logic_vector(31 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a decimal number
PROCEDURE print_now_s_dl(s: IN string;s2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, to_integer(unsigned(s2)));
WRITELINE(output,l);
END print_now_s_dl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic
PROCEDURE print_now_s_std(s: IN string; bit: IN std_logic) IS
VARIABLE l: line;
VARIABLE s2: string(1 TO 3);
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
IF bit = '1' THEN
s2 := "'1'";
ELSE
s2 := "'0'";
END IF;
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_now_s_std(s: IN string; vec: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, vec);
WRITELINE(output,l);
END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_now_s_std_s_std(s1: IN string; vec1: IN std_logic_vector;s2: IN string; vec2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s1);
HWRITE(l, vec1);
WRITE(l, s2);
HWRITE(l, vec2);
WRITELINE(output,l);
END print_now_s_std_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_now_s_std_s(s1: IN string; vec1: IN std_logic_vector;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s1);
HWRITE(l, vec1);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_std_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert character to std_logic_vector
FUNCTION char_to_std_logic_vector( arg : character) RETURN std_logic_vector IS
BEGIN
RETURN std_logic_vector(to_unsigned(character'POS(arg), 8));
END FUNCTION char_to_std_logic_vector;
----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert std_logic_vector to character
FUNCTION std_logic_vector_to_char( arg : std_logic_vector(7 DOWNTO 0) ) RETURN character IS
BEGIN
CASE arg IS
-- NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
-- BS, HT, LF, VT, FF, CR, SO, SI,
WHEN "00000000" =>
RETURN NUL;
WHEN "00000001" =>
RETURN SOH;
WHEN "00000010" =>
RETURN STX;
WHEN "00000011" =>
RETURN ETX;
WHEN "00000100" =>
RETURN EOT;
WHEN "00000101"=>
RETURN ENQ;
WHEN "00000110" =>
RETURN ACK;
WHEN "00000111" =>
RETURN BEL;
WHEN "00001000" =>
RETURN BS;
WHEN "00001001" =>
RETURN HT;
WHEN "00001010" =>
RETURN LF;
WHEN "00001011" =>
RETURN VT;
WHEN "00001100" =>
RETURN FF;
WHEN "00001101" =>
RETURN CR;
WHEN "00001110" =>
RETURN SO;
WHEN "00001111" =>
RETURN SI;
-- DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
-- CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
WHEN "00010000" =>
RETURN DLE;
WHEN "00010001" =>
RETURN DC1;
WHEN "00010010" =>
RETURN DC2;
WHEN "00010011" =>
RETURN DC3;
WHEN "00010100" =>
RETURN DC4;
WHEN "00010101" =>
RETURN NAK;
WHEN "00010110" =>
RETURN SYN;
WHEN "00010111" =>
RETURN ETB;
WHEN "00011000" =>
RETURN CAN;
WHEN "00011001" =>
RETURN EM;
WHEN "00011010" =>
RETURN SUB;
WHEN "00011011" =>
RETURN ESC;
WHEN "00011100" =>
RETURN FSP;
WHEN "00011101" =>
RETURN GSP;
WHEN "00011110" =>
RETURN RSP;
WHEN "00011111" =>
RETURN USP;
-- ' ', '!', '"', '#', '$', '%', '&', ''',
-- '(', ')', '*', '+', ',', '-', '.', '/',
WHEN "00100000" =>
RETURN ' ';
WHEN "00100001" =>
RETURN '!';
WHEN "00100010" =>
RETURN '"'; --"
WHEN "00100011" =>
RETURN '#';
WHEN "00100100" =>
RETURN '$';
WHEN "00100101" =>
RETURN '%';
WHEN "00100110" =>
RETURN '&';
WHEN "00100111" =>
RETURN ''';
WHEN "00101000" =>
RETURN '(';
WHEN "00101001" =>
RETURN ')';
WHEN "00101010" =>
RETURN '*';
WHEN "00101011" =>
RETURN '+';
WHEN "00101100" =>
RETURN ',';
WHEN "00101101" =>
RETURN '-';
WHEN "00101110" =>
RETURN '.';
WHEN "00101111" =>
RETURN '/';
-- '0', '1', '2', '3', '4', '5', '6', '7',
-- '8', '9', ':', ';', '<', '=', '>', '?',
WHEN "00110000" =>
RETURN '0';
WHEN "00110001" =>
RETURN '1';
WHEN "00110010" =>
RETURN '2';
WHEN "00110011" =>
RETURN '3';
WHEN "00110100" =>
RETURN '4';
WHEN "00110101" =>
RETURN '5';
WHEN "00110110" =>
RETURN '6';
WHEN "00110111" =>
RETURN '7';
WHEN "00111000" =>
RETURN '8';
WHEN "00111001" =>
RETURN '9';
WHEN "00111010" =>
RETURN ':';
WHEN "00111011" =>
RETURN ';';
WHEN "00111100" =>
RETURN '<';
WHEN "00111101" =>
RETURN '=';
WHEN "00111110" =>
RETURN '>';
WHEN "00111111" =>
RETURN '?';
-- '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
-- 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
WHEN "01000000" =>
RETURN '@';
WHEN "01000001" =>
RETURN 'A';
WHEN "01000010" =>
RETURN 'B';
WHEN "01000011" =>
RETURN 'C';
WHEN "01000100" =>
RETURN 'D';
WHEN "01000101" =>
RETURN 'E';
WHEN "01000110" =>
RETURN 'F';
WHEN "01000111" =>
RETURN 'G';
WHEN "01001000" =>
RETURN 'H';
WHEN "01001001" =>
RETURN 'I';
WHEN "01001010" =>
RETURN 'J';
WHEN "01001011" =>
RETURN 'K';
WHEN "01001100" =>
RETURN 'L';
WHEN "01001101" =>
RETURN 'M';
WHEN "01001110" =>
RETURN 'N';
WHEN "01001111" =>
RETURN 'O';
-- 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
-- 'X', 'Y', 'Z', '[', '\', ']', '^', '_',
WHEN "01010000" =>
RETURN 'P';
WHEN "01010001" =>
RETURN 'Q';
WHEN "01010010" =>
RETURN 'R';
WHEN "01010011" =>
RETURN 'S';
WHEN "01010100" =>
RETURN 'T';
WHEN "01010101" =>
RETURN 'U';
WHEN "01010110" =>
RETURN 'V';
WHEN "01010111" =>
RETURN 'W';
WHEN "01011000" =>
RETURN 'X';
WHEN "01011001" =>
RETURN 'Y';
WHEN "01011010" =>
RETURN 'Z';
WHEN "01011011" =>
RETURN '[';
WHEN "01011100" =>
RETURN '\';
WHEN "01011101" =>
RETURN ']';
WHEN "01011110" =>
RETURN '^';
WHEN "01011111" =>
RETURN '_';
-- '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
-- 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
WHEN "01100000" =>
RETURN '`';
WHEN "01100001" =>
RETURN 'a';
WHEN "01100010" =>
RETURN 'b';
WHEN "01100011" =>
RETURN 'c';
WHEN "01100100" =>
RETURN 'd';
WHEN "01100101" =>
RETURN 'e';
WHEN "01100110" =>
RETURN 'f';
WHEN "01100111" =>
RETURN 'g';
WHEN "01101000" =>
RETURN 'h';
WHEN "01101001" =>
RETURN 'i';
WHEN "01101010" =>
RETURN 'j';
WHEN "01101011" =>
RETURN 'k';
WHEN "01101100" =>
RETURN 'l';
WHEN "01101101" =>
RETURN 'm';
WHEN "01101110" =>
RETURN 'n';
WHEN "01101111" =>
RETURN 'o';
-- 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
-- 'x', 'y', 'z', '{', '|', '}', '~', DEL,
WHEN "01110000" =>
RETURN 'p';
WHEN "01110001" =>
RETURN 'q';
WHEN "01110010" =>
RETURN 'r';
WHEN "01110011" =>
RETURN 's';
WHEN "01110100" =>
RETURN 't';
WHEN "01110101" =>
RETURN 'u';
WHEN "01110110" =>
RETURN 'v';
WHEN "01110111" =>
RETURN 'w';
WHEN "01111000" =>
RETURN 'x';
WHEN "01111001" =>
RETURN 'y';
WHEN "01111010" =>
RETURN 'z';
WHEN "01111011" =>
RETURN '{';
WHEN "01111100" =>
RETURN '|';
WHEN "01111101" =>
RETURN '}';
WHEN "01111110" =>
RETURN '~';
WHEN "01111111" =>
RETURN DEL;
WHEN OTHERS =>
RETURN '0';
END CASE;
-- missing characters:
-- C128, C129, C130, C131, C132, C133, C134, C135,
-- C136, C137, C138, C139, C140, C141, C142, C143,
-- C144, C145, C146, C147, C148, C149, C150, C151,
-- C152, C153, C154, C155, C156, C157, C158, C159,
-- ' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
-- '¨', '©', 'ª', '«', '¬', '­', '®', '¯',
-- '°', '±', '²', '³', '´', 'µ', '¶', '·',
-- '¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
-- 'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
-- 'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
-- 'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
-- 'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
-- 'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
-- 'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
-- 'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
-- 'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ');
END FUNCTION std_logic_vector_to_char;
END;
\ No newline at end of file
#
# Create work library
#
vlib work
#
# Compile sources
#
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/fastevent_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
vcom -explicit -93 "./print_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
vcom -explicit -93 "../top/conv_ttl_rs485.vhd"
vcom -explicit -93 "./testbench_pkg.vhd"
vcom -explicit -93 "./i2c_master_and_driver.vhd"
vcom -explicit -93 "./i2c_bus_model.vhd"
vcom -explicit -93 "./testbench.vhd"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ns -lib work work.testbench
#
# Source the wave do file
#
do {testbench_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {testbench.udo}
#
# Run simulation for this time
#
run 2 ms
#
# End
#
\ No newline at end of file
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Converter Common Gateware
-- https://www.ohwr.org/projects/conv-common-gw
--------------------------------------------------------------------------------
--
-- unit name: Top-level simulation of conv_common_gw
--
-- description:
--
--
--
--------------------------------------------------------------------------------
-- Copyright (c) 2010-2012 CERN / BE-CO-HT
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.conv_common_gw_pkg.all;
use work.testbench_pkg.all;
use work.print_pkg.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Functions and procedures
--============================================================================
--============================================================================
-- Signal declarations
--============================================================================
signal i2c_m_in : t_i2c_master_in;
signal i2c_m_out : t_i2c_master_out;
signal clk_20, clk_125 : std_logic;
signal clk_125_p, clk_125_n : std_logic;
signal vme_sysreset_n : std_logic := '0';
signal ttl_n_in, ttl_out : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '1');
signal rs485_n_in, rs485_fs_n_in : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '1');
signal rs485_out : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '1');
signal inv_n_in, inv_out : std_logic_vector(C_NR_INV_CHANS-1 downto 0) := (others => '0');
signal sscl_out : std_logic;
signal sscl_en_out : std_logic;
signal ssda_out : std_logic;
signal ssda_en_out : std_logic;
signal mscl_out : std_logic;
signal mscl_en_out : std_logic;
signal msda_out : std_logic;
signal msda_en_out : std_logic;
signal sw_gp_n_in : std_logic_vector(7 downto 0);
signal sw_other_in : std_logic_vector(31 downto 0);
signal pcbrev : std_logic_vector(5 downto 0);
signal rtm_in : std_logic_vector(5 downto 0);
signal i2c_master_rcvd_val : std_logic_vector(31 downto 0);
signal i2c_master_rcvd_val1 : std_logic_vector(31 downto 0);
signal mscl, msda : std_logic_vector(C_NR_MASTERS-1 downto 0);
signal sscl, ssda : std_logic_vector(C_NR_SLAVES-1 downto 0);
signal scl, sda : std_logic;
signal rst_copm : std_logic;
type cnt_ch_array is array (C_NR_CHANS-1 downto 0) of integer;
signal fp_rp_same, fp_rp_oppos : cnt_ch_array;
signal in_out_oppos, in_out_same : cnt_ch_array;
signal pulse_cnt_ttl, pulse_cnt_rs485 : cnt_ch_array;
signal inv_err : cnt_ch_array;
type cnt_inv_ch_array is array (C_NR_INV_CHANS-1 downto 0) of integer;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Instantiate DUT
--============================================================================
cmp_DUT: conv_ttl_rs485
generic map (g_simul => false)
port map
(
-- Clocks
clk_20_i => clk_20,
clk_125_p_i => clk_125_p,
clk_125_n_i => clk_125_n,
-- I2C interface
scl_i => scl,
scl_o => sscl_out,
scl_en_o => sscl_en_out,
sda_i => sda,
sda_o => ssda_out,
sda_en_o => ssda_en_out,
-- VME interface
vme_sysreset_n_i => vme_sysreset_n,
vme_ga_i => "11110", --
vme_gap_i => '0',
-- PCB version recognition
pcbrev_i => pcbrev,
-- Channel enable
global_oen_o => open,
ttl_oen_o => open,
inv_oen_o => open,
rs485_oen_o => open,
-- Front panel channels
ttl_n_i => ttl_n_in,
ttl_o => ttl_out,
inv_n_i => inv_n_in,
inv_o => inv_out,
-- Rear panel channels
rs485_n_i => rs485_n_in,
rs485_fs_n_i => rs485_fs_n_in,
rs485_o => rs485_out,
-- Rear input and output termination lines
iterm_en_o => open,
oterm_en_o => open,
-- Channel leds
led_front_n_o => open,
led_front_inv_n_o => open,
led_rear_n_o => open,
-- SPI interface to on-board flash chip
flash_cs_n_o => open,
flash_sclk_o => open,
flash_mosi_o => open,
flash_miso_i => 'Z',
-- PLL DACs
dac20_din_o => open,
dac20_sclk_o => open,
dac20_sync_n_o => open,
dac125_din_o => open,
dac125_sclk_o => open,
dac125_sync_n_o => open,
-- SFP lines
sfp_los_i => '1',
sfp_present_i => '0',
sfp_rate_select_o => open,
sfp_sda_b => open,
sfp_scl_b => open,
sfp_tx_disable_o => open,
sfp_tx_fault_i => '1',
-- Thermometer data port
thermometer_b => open,
-- Switches
sw_gp_n_i => sw_gp_n_in,
sw_multicast_n_i => (others => '0'), -- not used
-- RTM lines
rtmm_i => rtm_in(5 downto 3),
rtmp_i => rtm_in(2 downto 0),
-- Front panel bicolor LEDs
led_ctrl0_o => open,
led_ctrl0_oen_o => open,
led_ctrl1_o => open,
led_ctrl1_oen_o => open,
led_gp_2_4_o => open,
led_gp_1_3_o => open,
led_oterm_wr_o => open,
led_iterm_syserror_o => open,
led_gf_syspw_o => open,
led_ttl_i2c_o => open);
sscl(0) <= sscl_out when (sscl_en_out = '1') else '1';
ssda(0) <= ssda_out when (ssda_en_out = '1') else '1';
--============================================================================
-- Generate clock and reset signals
--============================================================================
p_clk_20 : process
begin
clk_20 <= '0';
wait for C_CLK_20_PER/2;
clk_20 <= '1';
wait for C_CLK_20_PER/2;
end process;
p_clk_125 : process
begin
clk_125 <= '0';
wait for C_CLK_125_PER/2;
clk_125 <= '1';
wait for C_CLK_125_PER/2;
end process;
clk_125_p <= clk_125;
clk_125_n <= not clk_125;
p_vme_sysreset_n: process
begin
vme_sysreset_n <= '0';
wait for c_reset_width;
vme_sysreset_n <= '1';
wait for c_reset_width;
vme_sysreset_n <= '0';
wait for c_reset_width;
vme_sysreset_n <= '1';
wait;
end process p_vme_sysreset_n;
--============================================================================
-- Instantiate I2C master to access DUT
--============================================================================
cmp_i2c_master_and_driver: entity work.i2c_master_and_driver
port map (
clk_i => clk_20,
rst_n_i => vme_sysreset_n,
ready_o => i2c_m_out.i2c_master_ready,
start_i => i2c_m_in.i2c_master_start,
finish_o => i2c_m_out.i2c_master_finish,
rdwr_i => i2c_m_in.i2c_master_rdwr,
slv_addr_i => i2c_m_in.i2c_master_slv_addr,
reg_addr_i => i2c_m_in.i2c_master_reg_addr,
send_val_i => i2c_m_in.i2c_master_send_val,
rcvd_val_o => i2c_m_out.i2c_master_rcvd_val,
scl_i => scl,
scl_o => mscl_out,
scl_oen => mscl_en_out,
sda_i => sda,
sda_o => msda_out,
sda_oen => msda_en_out
);
-- Tri-state buffers on the I2C lines
mscl(0) <= mscl_out when (mscl_en_out = '0') else '1';
msda(0) <= msda_out when (msda_en_out = '0') else '1';
--============================================================================
-- Bus model connection to master and slaves
--============================================================================
cmp_i2c_bus : entity work.i2c_bus_model
generic map(
g_nr_masters => C_NR_MASTERS,
g_nr_slaves => C_NR_SLAVES
)
port map (
mscl_i => mscl,
msda_i => msda,
sscl_i => sscl,
ssda_i => ssda,
scl_o => scl,
sda_o => sda
);
--============================================================================
-- Check if ttl_out matches rs485_out
--============================================================================
compare_front_rear_pulses: process (clk_125)
begin
if rising_edge (clk_125) then
if vme_sysreset_n = '0' or rst_copm = '1' then
fp_rp_same <= (others=> (0));
fp_rp_oppos <= (others=> (0));
in_out_same <= (others=> (0));
in_out_oppos <= (others=> (0));
else
for i in 0 to C_NR_CHANS-1 loop
if ttl_out(i) /= rs485_out(i) then
fp_rp_same(i) <= fp_rp_same(i)+1;
end if;
if ttl_out(i) /= not rs485_out(i) then
fp_rp_oppos(i) <= fp_rp_oppos(i)+1;
end if;
if ttl_out(i) /= not ttl_n_in(i) then
in_out_oppos(i) <= in_out_oppos(i)+1;
end if;
if ttl_out(i) /= ttl_n_in(i) then
in_out_same(i) <= in_out_same(i)+1;
end if;
end loop;
end if;
end if;
end process;
--============================================================================
-- Check INV channels
--============================================================================
compare_inv_i_inv_o: process (clk_125)
begin
if rising_edge (clk_125) then
if vme_sysreset_n = '0' then
inv_err <= (others=> (0));
else
for i in 0 to C_NR_INV_CHANS-1 loop
if inv_n_in(i) /= inv_out(i) then
inv_err(i) <= inv_err(i)+1;
end if;
end loop;
end if;
end if;
end process;
--============================================================================
-- pulse counter
--============================================================================
pulse_counter_ttl: process (ttl_out)
begin
if vme_sysreset_n = '0' then
pulse_cnt_ttl <= (others=> (0));
end if;
--for i in 0 to C_NR_CHANS-1 loop
if rising_edge(ttl_out(0)) then
pulse_cnt_ttl(0) <= pulse_cnt_ttl(0) +1;
end if;
if rising_edge(ttl_out(1)) then
pulse_cnt_ttl(1) <= pulse_cnt_ttl(1) +1;
end if;
if rising_edge(ttl_out(2)) then
pulse_cnt_ttl(2) <= pulse_cnt_ttl(2) +1;
end if;
if rising_edge(ttl_out(3)) then
pulse_cnt_ttl(3) <= pulse_cnt_ttl(3) +1;
end if;
if rising_edge(ttl_out(4)) then
pulse_cnt_ttl(4) <= pulse_cnt_ttl(4) +1;
end if;
if rising_edge(ttl_out(5)) then
pulse_cnt_ttl(5) <= pulse_cnt_ttl(5) +1;
end if;
--end loop;
end process pulse_counter_ttl;
pulse_counter_rs485: process (rs485_out)
begin
if vme_sysreset_n = '0' then
pulse_cnt_rs485 <= (others=> (0));
end if;
--for i in 0 to C_NR_CHANS-1 loop
if rising_edge(rs485_out(0)) then
pulse_cnt_rs485(0) <= pulse_cnt_rs485(0) +1;
end if;
if rising_edge(rs485_out(1)) then
pulse_cnt_rs485(1) <= pulse_cnt_rs485(1) +1;
end if;
if rising_edge(rs485_out(2)) then
pulse_cnt_rs485(2) <= pulse_cnt_rs485(2) +1;
end if;
if rising_edge(rs485_out(3)) then
pulse_cnt_rs485(3) <= pulse_cnt_rs485(3) +1;
end if;
if rising_edge(rs485_out(4)) then
pulse_cnt_rs485(4) <= pulse_cnt_rs485(4) +1;
end if;
if rising_edge(rs485_out(5)) then
pulse_cnt_rs485(5) <= pulse_cnt_rs485(5) +1;
end if;
--end loop;
end process pulse_counter_rs485;
--============================================================================
-- processes to provide stimulus and checks
--============================================================================
--i2c access
p_stim : process
variable i : integer := 0;
variable nb_pulses_to_send_fp : integer := 17;
variable nb_pulses_to_send_fp_slv : std_logic_vector(31 downto 0);
variable nb_pulses_to_send_rp : integer := 5;
variable nb_pulses_to_send_rp_slv : std_logic_vector(31 downto 0);
variable nb_pulses_to_send_inv : integer := 5;
variable nb_pulses_to_send_bar : integer := 6;
variable glitch_filter_en : std_logic := '0'; -- glitch filter disabled
variable ttl_out_bar_en : std_logic := '0'; -- TTLbar disabled
variable err_cnt, err : integer := 0;
variable time_intrvl, rst_timetag : integer := 0;
variable pulse_timetag : integer := 0;
constant K : time := 1 nS;
begin
print("*****************************************************************************");
print(" Start of Tests");
print("*****************************************************************************");
---------------------------------------------------------------------------
-- Board settings
print_now("----------------------------------------------------------------");
print_now("---> Configure board settings");
settings_config (glitch_filter_en, ttl_out_bar_en, sw_gp_n_in, sw_other_in, pcbrev, rtm_in);
---------------------------------------------------------------------------
-- VME reset
print_now("----------------------------------------------------------------");
print_now("---> VME reset");
print_now("Sending VME reset");
wait until vme_sysreset_n = '1';
print_now("VME reset completed");
wait for 6500 ns; -- for resets and inhibit_pulse to have finished
rst_timetag := now/K;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- I2C readings
print_now("----------------------------------------------------------------");
print_now("---> Test 01: I2C reg reading");
print_now("----------------------------------------------------------------");
-- I2C reading of the board ID register
print_now_s("I2C reading of the register ", c_REG_MAP(0).reg_name);
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(0).reg_addr, c_REG_MAP(0).reg_name, i2c_master_rcvd_val, C_BOARD_ID, TRUE, err);
err_cnt := err_cnt +err;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
-- I2C writing
print_now("----------------------------------------------------------------");
print_now("---> Test 02: I2C reg writing");
print_now("----------------------------------------------------------------");
-- I2C writing of a big value to Front Panel Counter 1
print_now_s("I2C writing to the register ", c_REG_MAP(4).reg_name);
write_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(4).reg_addr, c_REG_MAP(4).reg_name, C_INITIAL_TST_VALUE, err);
err_cnt := err_cnt +err;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
-- Pulses to the front TTL input
print_now("----------------------------------------------------------------");
print_now("---> Test 03: Sending TTL pulses and checking the outputs");
print_now("----------------------------------------------------------------");
-- Sending pulses to Front Panel Channel 1
nb_pulses_to_send_fp_slv := std_logic_vector(to_unsigned(nb_pulses_to_send_fp, nb_pulses_to_send_fp_slv'length));
print_now_s_i("Sending TTL pulses to TTL_N_I(0)", nb_pulses_to_send_fp);
generate_pulse (ttl_n_in(0), nb_pulses_to_send_fp, "fp", rs485_fs_n_in(0), 200ns, 200ns); -- 200ns so that the counters can count correctly
-- Checking if the number of TTL output pulses matches the sent ones
print_now("Check that the pulses arrived to the TTL_O(0)");
if pulse_cnt_ttl(0) = nb_pulses_to_send_fp then
print_now_s_i("[OK] Number of pulses measured at TTL_O(0): ",pulse_cnt_ttl(0));
else
print_now_s_i("[ERR] Number of pulses measured at TTL_O(0): ",pulse_cnt_ttl(0));
err_cnt := err_cnt + 1;
end if;
-- Check if TTL_N_IN out and TTL_O out are opposite
print_now("Check that TTL_O(0) is the inverted TTL_N_IN(0)");
if in_out_oppos(0) = 0 then
print_now("[OK] TTL_O(0) is exactly the inverted TTL_N_IN(0)");
else
print_now("[ERR] TTL_O(0) is not exactly the inverted TTL_N_IN(0)");
err_cnt := err_cnt + 1;
end if;
-- Check if TTL out and RS485 out are the same
print_now("Check that the pulses arrived to the RS485_O(0)");
if fp_rp_same(0) = 0 then
print_now("[OK] RS485_O(0) matches TTL_O(0)");
else
print_now("[ERR] RS485_O(0) does not match TTL_O(0)");
err_cnt := err_cnt + 1;
end if;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
-- Counters reading
print_now("----------------------------------------------------------------");
print_now("---> Test 04: Reading of the pulse counters through I2C");
print_now("----------------------------------------------------------------");
-- Reading from the I2C Front Panel regs; read only two counters to speed up testbench
while not(i = 3) loop
if i = 0 then
-- Front Panel Channel 1 register should roll over and read
print_now_s("I2C reading of the register ", c_REG_MAP(i+4).reg_name);
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(i+4).reg_addr, c_REG_MAP(i+4).reg_name , i2c_master_rcvd_val, std_logic_vector(unsigned(C_INITIAL_TST_VALUE)+unsigned(nb_pulses_to_send_fp_slv)), TRUE, err);
err_cnt := err_cnt + err;
elsif i = 1 then
-- Front Panel Channel 2 register should have not counted any pulses
print_now_s("I2C reading of the register ", c_REG_MAP(i+4).reg_name);
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(i+4).reg_addr, c_REG_MAP(i+4).reg_name, i2c_master_rcvd_val, (others =>'0'), TRUE, err);
err_cnt := err_cnt + err;
end if;
i := i + 1;
end loop;
print_now("Checking that the rear pulse counters have not registered any pulses");
-- Reading from the I2C Rear Panel regs; read only two counters to speed up testbench
i := 0;
while not(i = 2) loop
if i = 0 then
-- Check Rear Panel Channel 1 counter has not counted any pulses
print_now_s("I2C reading of the register ", c_REG_MAP(i+10).reg_name);
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(i+10).reg_addr, c_REG_MAP(i+10).reg_name , i2c_master_rcvd_val, (others =>'0'), TRUE, err);
err_cnt := err_cnt + err;
elsif i = 1 then
-- Check Rear Panel Channel 1 counter has not counted any pulses
print_now_s("I2C reading of the register ", c_REG_MAP(i+10).reg_name);
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(i+10).reg_addr, c_REG_MAP(i+10).reg_name, i2c_master_rcvd_val, (others =>'0'), TRUE, err);
err_cnt := err_cnt + err;
end if;
i := i + 1;
end loop;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
-- Pulses to the rear RS485 input
print_now("----------------------------------------------------------------");
print_now("---> Test 05: Sending pulses to the RS485 and checking the outputs");
print_now("----------------------------------------------------------------");
-- Sending pulses to Rear Panel Channel 1
nb_pulses_to_send_rp := 5;
nb_pulses_to_send_rp_slv := std_logic_vector(to_unsigned(nb_pulses_to_send_rp, nb_pulses_to_send_rp_slv'length));
print_now_s_i("Sending pulses to RS485_N_I(0): ", nb_pulses_to_send_rp);
generate_pulse (rs485_n_in(0), nb_pulses_to_send_rp, "rp", rs485_fs_n_in(0), 200ns, 200ns);
pulse_timetag := (now/K);
-- Checking if the number of RS485 output pulses matches the sent ones
print_now("Check that the pulses arrived to the RS485_O(0)");
if pulse_cnt_rs485(0) = nb_pulses_to_send_rp+nb_pulses_to_send_fp then
print_now_s_i("[OK] Number of pulses measured at RS485_O(0) :",pulse_cnt_rs485(0));
else
print_now_s_i("[ERR] Number of pulses measured in the RS485_O(0) : ",pulse_cnt_rs485(0));
err_cnt := err_cnt + 1;
end if;
-- Check if TTL out and RS485 out are the same
print_now("Check that the pulses arrived to the TTL_O(0)");
if fp_rp_same(0) = 0 then
print_now("[OK] RS485_O(0) matches TTL_O(0)");
else
print_now("[ERR] RS485_O(0) does not match TTL_O(0)");
err_cnt := err_cnt + 1;
end if;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
-- Counters reading
print_now("----------------------------------------------------------------");
print_now("---> Test 06: Reading of the pulse counters through I2C");
print_now("----------------------------------------------------------------");
---------------------------------------------------------------------------
-- Reading from the I2C Rear Panel regs; read two reg to speed up testbench
i := 0;
while not(i = 2) loop
if i = 0 then
-- Check Rear Panel Channel 1 counter has correctly counted the pulses
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(i+10).reg_addr, c_REG_MAP(i+10).reg_name , i2c_master_rcvd_val, nb_pulses_to_send_rp_slv, TRUE, err);
err_cnt := err_cnt + err;
elsif i = 1 then
-- Check Rear Panel Channel 2 has not counted any pulses
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(i+10).reg_addr, c_REG_MAP(i+10).reg_name, i2c_master_rcvd_val, (others =>'0'), TRUE, err);
err_cnt := err_cnt + err;
end if;
i := i + 1;
end loop;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
-- Timetag reading
print_now("----------------------------------------------------------------");
print_now("---> Test 07: Reading of the timetag register through I2C");
print_now("----------------------------------------------------------------");
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, CH1LTSCYR, "CH1LTSCY", i2c_master_rcvd_val1, (others =>'0'), FALSE, err);
time_intrvl := (pulse_timetag - rst_timetag)/8;
print_now_s_i("Estimated timetag cycles: ",time_intrvl);
if to_integer(unsigned(i2c_master_rcvd_val1(27 downto 0))) > time_intrvl+1000 or to_integer(unsigned(i2c_master_rcvd_val1(27 downto 0))) < time_intrvl-1000 then
print_now_s_std_s_std("[ERR] Registered cycles: ", i2c_master_rcvd_val1, " is far from the estimated: ", std_logic_vector(to_unsigned(time_intrvl,28)));
err_cnt := err_cnt + 1;
else
print_now_s_std_s_std("[OK] Registered cycles: ", i2c_master_rcvd_val1(27 downto 0), " is close to the estimated: ", std_logic_vector(to_unsigned(time_intrvl,28)));
end if;
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, CH1LTSTLR, "CH1LTSTL", i2c_master_rcvd_val, (others =>'0'), TRUE, err);
err_cnt := err_cnt + err;
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, CH1LTSCYR, "CH1LTSCY", i2c_master_rcvd_val, i2c_master_rcvd_val1, TRUE, err);
err_cnt := err_cnt + err;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
-- INV channels
print_now("----------------------------------------------------------------");
print_now("---> Test 08: INV channel check");
print_now("----------------------------------------------------------------");
-- Note INV channels just take INV_N_I and output the same signal to INV_O;
-- inversion happens through inv buffers; there is no associated counter, timetag, rear channel
print_now_s_i("Sending pulses to INV_N_I(3): ", nb_pulses_to_send_inv);
generate_pulse (inv_n_in(3), nb_pulses_to_send_inv, "fp", rs485_fs_n_in(3), 40ns, 20ns);
print_now("Check INV_O(3) output");
if inv_err(3) = 0 then
print_now("[OK] INV_O(3) matches INV_N_I(3)");
else
print_now("[ERR] INV_O(3) does not match INV_N_I(3)");
err_cnt := err_cnt + 1;
end if;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
-- Glitch filter test
print_now("----------------------------------------------------------------");
print_now("---> Test 09: Test Glitch filter");
print_now("----------------------------------------------------------------");
---------------------------------------------------------------------------
-- Change board settings
print_now("---> Configure board settings");
glitch_filter_en := '1';
ttl_out_bar_en := '0';
settings_config (glitch_filter_en, ttl_out_bar_en, sw_gp_n_in, sw_other_in, pcbrev, rtm_in);
wait for 2 us; -- ML: does not work without this wait, no idea way?
print_now_s_i("Sending pulses 50ns-long each to TTL_N_I(3): ", nb_pulses_to_send_fp);
generate_pulse (ttl_n_in(3), nb_pulses_to_send_fp, "fp", rs485_fs_n_in(3), 50ns, 20ns);
-- Checking if any pulse was passed to the output
print_now("Check that the glitches were filtered and there is no pulse in the TTL_O(3) output");
if pulse_cnt_ttl(3) = 0 then
print_now("[OK] Glitch filter filtered the glitches");
else
print_now_s_i("[ERR] Number of pulses measured at TTL_O(3): ",pulse_cnt_ttl(3));
err_cnt := err_cnt + 1;
end if;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
-- TTL bar test
print_now("----------------------------------------------------------------");
print_now("---> Test 10: Test TTL BAR");
print_now("----------------------------------------------------------------");
---------------------------------------------------------------------------
-- Change board settings
print_now("---> Configure board settings");
glitch_filter_en := '0';
ttl_out_bar_en := '1';
settings_config (glitch_filter_en, ttl_out_bar_en, sw_gp_n_in, sw_other_in, pcbrev, rtm_in);
rst_copm <= '1';
wait for 2 us; -- ML: does not work without this wait, no idea way?
rst_copm <= '0';
generate_pulse (ttl_n_in(5), nb_pulses_to_send_bar, "fp", rs485_fs_n_in(5), 200ns, 200ns);
-- Check if TTL_N_IN out and TTL_O out are the same
print_now("Check that TTL_O(5) matches TTL_N_IN(5)");
if in_out_same(5) = 0 then
print_now("[OK] TTL_O(5) matches TTL_N_IN(5)");
else
print_now("[ERR] TTL_O(5) does not match TTL_N_IN(5)");
err_cnt := err_cnt + 1;
end if;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
print("*****************************************************************************");
print(" Tests Summary");
print("*****************************************************************************");
print_now_s_i("Total number of errors: ", err_cnt);
print("*****************************************************************************");
wait for 500 us;
end process p_stim;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
--==============================================================================
-- CERN (BE-CO-HT)
-- TTL-RS485 pkg package
--==============================================================================
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.print_pkg.all;
package testbench_pkg is
--============================================================================
-- Constant declarations
--============================================================================
-- Clock periods
constant C_CLK_20_PER : time := 50 ns;
constant C_CLK_125_PER : time := 8 ns;
constant C_RESET_WIDTH : time := 200 ns;
-- DUT configuration (generics):
constant C_NR_CHANS : integer := 6;
constant C_NR_INV_CHANS : integer := 4;
constant C_BOARD_ID : std_logic_vector(31 downto 0) := x"54343835";
-- Number of I2C masters and slaves for the I2C bus model
constant C_NR_MASTERS : positive := 1;
constant C_NR_SLAVES : positive := 1;
constant C_RTM : std_logic_vector(5 downto 0) := "010101";
constant C_INITIAL_TST_VALUE : std_logic_vector(31 downto 0) := x"FFFFFFF0";
constant C_I2C_MASTER_SLV_ADDR: std_logic_vector(6 downto 0) := "1011110";
-- DUT register map:
constant C_BIDR : std_logic_vector(31 downto 0) := x"00000000";
constant C_SR : std_logic_vector(31 downto 0) := x"00000004";
constant C_ERR : std_logic_vector(31 downto 0) := x"00000008";
constant C_CR : std_logic_vector(31 downto 0) := x"0000000C";
constant C_CH1FPPCR : std_logic_vector(31 downto 0) := x"00000010";
constant C_CH2FPPCR : std_logic_vector(31 downto 0) := x"00000014";
constant C_CH3FPPCR : std_logic_vector(31 downto 0) := x"00000018";
constant C_CH4FPPCR : std_logic_vector(31 downto 0) := x"0000001C";
constant C_CH5FPPCR : std_logic_vector(31 downto 0) := x"00000020";
constant C_CH6FPPCR : std_logic_vector(31 downto 0) := x"00000024";
constant C_CH1RPPCR : std_logic_vector(31 downto 0) := x"00000028";
constant C_CH2RPPCR : std_logic_vector(31 downto 0) := x"0000002C";
constant C_CH3RPPCR : std_logic_vector(31 downto 0) := x"00000030";
constant C_CH4RPPCR : std_logic_vector(31 downto 0) := x"00000034";
constant C_CH5RPPCR : std_logic_vector(31 downto 0) := x"00000038";
constant C_CH6RPPCR : std_logic_vector(31 downto 0) := x"0000003C";
constant CH1LTSCYR : std_logic_vector(31 downto 0) := x"0000005C";
constant CH1LTSTLR : std_logic_vector(31 downto 0) := x"00000060";
type t_reg is
record
reg_addr : std_logic_vector(31 downto 0);
reg_name : string(1 to 8);
end record;
type t_reg_table is array (natural range <>) of t_reg;
constant c_REG_MAP : t_reg_table(15 downto 0) :=
(0 => (reg_addr => C_BIDR,
reg_name => "BIDR "),
1 => (reg_addr => C_SR,
reg_name => "SR "),
2 => (reg_addr => C_ERR,
reg_name => "ERR "),
3 => (reg_addr => C_CR,
reg_name => "CR "),
4 => (reg_addr => C_CH1FPPCR,
reg_name => "CH1FPPCR"),
5 => (reg_addr => C_CH2FPPCR,
reg_name => "CH3FPPCR"),
6 => (reg_addr => C_CH3FPPCR,
reg_name => "CH3FPPCR"),
7 => (reg_addr => C_CH4FPPCR,
reg_name => "CH4FPPCR"),
8 => (reg_addr => C_CH5FPPCR,
reg_name => "CH5FPPCR"),
9 => (reg_addr => C_CH6FPPCR,
reg_name => "CH6FPPCR"),
10 => (reg_addr => C_CH1RPPCR,
reg_name => "CH1RPPCR"),
11 => (reg_addr => C_CH2RPPCR,
reg_name => "CH3RPPCR"),
12 => (reg_addr => C_CH3RPPCR,
reg_name => "CH3RPPCR"),
13 => (reg_addr => C_CH4RPPCR,
reg_name => "CH4RPPCR"),
14 => (reg_addr => C_CH5RPPCR,
reg_name => "CH5RPPCR"),
15 => (reg_addr => C_CH6RPPCR,
reg_name => "CH6RPPCR"));
--============================================================================
-- Types declarations
--============================================================================
type t_i2c_master_in is record
i2c_master_start : std_logic;
i2c_master_rdwr : std_logic;
i2c_master_slv_addr : std_logic_vector(6 downto 0);
i2c_master_reg_addr : std_logic_vector(31 downto 0);
i2c_master_send_val : std_logic_vector(31 downto 0);
end record;
type t_i2c_master_out is record
i2c_master_ready : std_logic;
i2c_master_finish : std_logic;
i2c_master_rcvd_val : std_logic_vector(31 downto 0);
end record;
--============================================================================
-- Components declarations
--============================================================================
component conv_ttl_rs485 is
generic (g_simul : boolean := FALSE);
port
(
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable
global_oen_o : out std_logic;
ttl_oen_o : out std_logic;
inv_oen_o : out std_logic;
rs485_oen_o : out std_logic;
-- Front panel channels
ttl_n_i : in std_logic_vector(5 downto 0);
ttl_o : out std_logic_vector(5 downto 0);
inv_n_i : in std_logic_vector(3 downto 0);
inv_o : out std_logic_vector(3 downto 0);
-- Rear panel channels
rs485_n_i : in std_logic_vector(5 downto 0);
rs485_fs_n_i : in std_logic_vector(5 downto 0);
rs485_o : out std_logic_vector(5 downto 0);
-- Rear input and output termination lines
iterm_en_o : out std_logic_vector(5 downto 0);
oterm_en_o : out std_logic_vector(5 downto 0);
-- Channel leds
led_front_n_o : out std_logic_vector(5 downto 0);
led_front_inv_n_o : out std_logic_vector(3 downto 0);
led_rear_n_o : out std_logic_vector(5 downto 0);
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
dac20_sclk_o : out std_logic;
dac20_sync_n_o : out std_logic;
-- 125 MHz clock generator control
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_present_i : in std_logic;
sfp_rate_select_o : out std_logic;
sfp_scl_b : inout std_logic;
sfp_sda_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- Thermometer data port
thermometer_b : inout std_logic;
-- Switches
sw_gp_n_i : in std_logic_vector(7 downto 0);
sw_multicast_n_i : in std_logic_vector(3 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- Front panel bicolor LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_gp_2_4_o : out std_logic;
led_gp_1_3_o : out std_logic;
led_oterm_wr_o : out std_logic;
led_iterm_syserror_o : out std_logic;
led_gf_syspw_o : out std_logic;
led_ttl_i2c_o : out std_logic
);
end component conv_ttl_rs485;
-- procedure read_i2c (signal i2c_m_out : in t_i2c_master_out;
-- signal i2c_m_in : out t_i2c_master_in;
-- signal slv_addr : in std_logic_vector( 6 downto 0);
-- signal reg_addr : in std_logic_vector(31 downto 0);
-- signal rcvd_val : out std_logic_vector(31 downto 0));
procedure generate_pulse (signal pulse_n_out : out std_logic;
nb_of_pulses : in natural;
fp_or_rp : in string (1 to 2);
signal rs485_fs_n : out std_logic;
ns_on : in time;
ns_off : in time);
procedure settings_config (constant glitch_filter_en : in std_logic;
constant ttl_out_bar_en : in std_logic;
signal sw_gp_n : out std_logic_vector(7 downto 0);
signal sw_other : out std_logic_vector(31 downto 0);
signal pcbrev : out std_logic_vector(5 downto 0);
signal rtm : out std_logic_vector(5 downto 0));
procedure cnt_pulses (signal pulse_train : in std_logic;
signal nb_of_pulses_cnted : out natural;
nb_pulses_expected : in integer);
procedure write_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out : in t_i2c_master_out;
constant slv_addr : in std_logic_vector( 6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
constant send_val : in std_logic_vector(31 downto 0);
err : out natural);
procedure read_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out : in t_i2c_master_out;
constant slv_addr : in std_logic_vector(6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
signal rcvd_val : out std_logic_vector(31 downto 0);
constant exp_val : in std_logic_vector(31 downto 0);
constant eval_result : in boolean;
err : out natural);
-- procedure read_i2c_err (signal i2c_m_in : out t_i2c_master_in;
-- signal i2c_m_out : in t_i2c_master_out);
end testbench_pkg;
package body testbench_pkg is
--==================================================================================================
-- Procedures
--==================================================================================================
procedure settings_config (constant glitch_filter_en : in std_logic;
constant ttl_out_bar_en : in std_logic;
signal sw_gp_n : out std_logic_vector(7 downto 0);
signal sw_other : out std_logic_vector(31 downto 0);
signal pcbrev : out std_logic_vector(5 downto 0);
signal rtm : out std_logic_vector(5 downto 0)) is
begin
sw_gp_n(0) <= not glitch_filter_en;
if glitch_filter_en = '1' then
print_now("Glitch filter enabled");
else
print_now("Glitch filter disabled");
end if;
sw_gp_n(7) <= ttl_out_bar_en;
if ttl_out_bar_en = '1' then
print_now("TTL output BAR enabled");
else
print_now("TTL output BAR disabled");
end if;
--print_now_s_std("RTMP & RTMM set to x", C_RTM);
sw_gp_n(6 downto 1) <= (others => '0'); -- not used
sw_other <= (others => '0'); -- not used
pcbrev <= "111100"; -- not used
rtm <= C_RTM; -- not used
end procedure;
----------------------------------------------------------------------------------------------------
procedure generate_pulse (signal pulse_n_out : out std_logic;
nb_of_pulses : in natural;
fp_or_rp : in string (1 to 2);
signal rs485_fs_n : out std_logic;
ns_on : in time;
ns_off : in time) is
variable numb_cnt : natural;
begin
numb_cnt := 0;
while not(numb_cnt = nb_of_pulses) loop
if fp_or_rp = "fp" then
rs485_fs_n <= '0'; -- stays inactive
pulse_n_out <= '1';
wait for ns_off;
pulse_n_out <= '0';
wait for ns_on;
pulse_n_out <= '1';
else
pulse_n_out <= '1';
rs485_fs_n <= '0';
wait for ns_off;
pulse_n_out <= '0';
rs485_fs_n <= '1';
wait for ns_on;
pulse_n_out <= '1';
rs485_fs_n <= '0';
end if;
numb_cnt:= numb_cnt + 1;
end loop;
wait for 500ns; -- wait for all pulses to propagate to the output
end procedure generate_pulse;
----------------------------------------------------------------------------------------------------
procedure cnt_pulses (signal pulse_train : in std_logic;
signal nb_of_pulses_cnted : out integer;
nb_pulses_expected : in integer) is
variable pulse_cnt : integer :=0;
variable err_sum : integer:=0;
begin
if rising_edge(pulse_train) then
pulse_cnt := pulse_cnt +1;
end if;
nb_of_pulses_cnted <= pulse_cnt;
if pulse_cnt = nb_pulses_expected then
print_now_s_i("[OK] counted: ", pulse_cnt);
else
print_now_s_i("[ERR] counted: ", pulse_cnt);
end if;
end procedure cnt_pulses;
----------------------------------------------------------------------------------------------------
procedure read_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out: in t_i2c_master_out;
constant slv_addr : in std_logic_vector(6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
signal rcvd_val : out std_logic_vector(31 downto 0);
constant exp_val : in std_logic_vector(31 downto 0);
constant eval_result : in boolean;
err : out natural) is
variable err_cnt : natural := 0;
begin
print_now("---------------");
print_now("read_i2c: start");
i2c_m_in.i2c_master_start <= '0';
i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
i2c_m_in.i2c_master_slv_addr <= C_I2C_MASTER_SLV_ADDR;
i2c_m_in.i2c_master_reg_addr <= (others => '0');
i2c_m_in.i2c_master_send_val <= (others => '1');
wait for 1us;
i2c_m_in.i2c_master_slv_addr <= slv_addr;
i2c_m_in.i2c_master_reg_addr <= reg_addr;
i2c_m_in.i2c_master_start <= '1';
i2c_m_in.i2c_master_rdwr <= '1'; --0: write
wait for C_CLK_20_PER;
i2c_m_in.i2c_master_start <= '0';
wait until i2c_m_out.i2c_master_finish = '1';
rcvd_val <= i2c_m_out.i2c_master_rcvd_val;
print_now_s_std_s_std("I2C value read from 0x", reg_addr(7 downto 0),
" is 0x",i2c_m_out.i2c_master_rcvd_val);
wait until i2c_m_out.i2c_master_finish = '0';
print_now("read_i2c: completed");
if eval_result = TRUE then
if i2c_m_out.i2c_master_rcvd_val = exp_val then
print_now_s_s("[OK] Correct reading from reg ", reg_name, "; expected value matches read value");
else
print_now_s_std_s_std("[ERR]: Read value from " & reg_name & ": ", i2c_m_out.i2c_master_rcvd_val,
"; expected value: ",exp_val);
err_cnt := err_cnt +1;
end if;
end if;
err := err_cnt;
print_now("---------------");
end procedure read_i2c;
----------------------------------------------------------------------------------------------------
procedure write_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out : in t_i2c_master_out;
constant slv_addr : in std_logic_vector( 6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
constant send_val : in std_logic_vector(31 downto 0);
err : out natural) is
variable err_cnt : natural := 0;
begin
print_now("---------------");
print_now("write_i2c: start");
i2c_m_in.i2c_master_start <= '0';
i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
i2c_m_in.i2c_master_slv_addr <= C_I2C_MASTER_SLV_ADDR;
i2c_m_in.i2c_master_reg_addr <= (others => '0');
i2c_m_in.i2c_master_send_val <= (others => '1');
wait for 1us;
i2c_m_in.i2c_master_slv_addr <= slv_addr;
i2c_m_in.i2c_master_reg_addr <= reg_addr;
i2c_m_in.i2c_master_send_val <= send_val;
i2c_m_in.i2c_master_start <= '1';
i2c_m_in.i2c_master_rdwr <= '0'; --0: write
wait for C_CLK_20_PER;
i2c_m_in.i2c_master_start <= '0';
wait until i2c_m_out.i2c_master_ready = '1';
print_now_s_std_s("write_i2C: Value ", send_val, " written to reg " & reg_name);
print_now("---------------");
err := 0;
end procedure write_i2c;
----------------------------------------------------------------------------------------------------
end;
-----------------------------------------------------------------------------------
......@@ -54,6 +54,7 @@
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
......@@ -67,8 +68,11 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Do File Behavioral" xil_pn:value="../../sim/tb_run.do" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
......@@ -81,6 +85,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -93,6 +98,7 @@
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -102,9 +108,9 @@
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -119,10 +125,12 @@
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -130,18 +138,26 @@
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<<<<<<< HEAD
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_rs485|arch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/conv_ttl_rs485.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_rs485" xil_pn:valueState="non-default"/>
=======
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gc_frequency_meter|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gc_frequency_meter" xil_pn:valueState="non-default"/>
>>>>>>> EG_sim
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -149,13 +165,21 @@
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<<<<<<< HEAD
=======
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
>>>>>>> EG_sim
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
......@@ -163,6 +187,8 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
......@@ -193,10 +219,13 @@
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="gc_frequency_meter" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -210,15 +239,17 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_rs485_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_rs485_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_rs485_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_rs485_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="gc_frequency_meter_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="gc_frequency_meter_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="gc_frequency_meter_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="gc_frequency_meter_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -235,7 +266,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="gc_frequency_meter" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -256,7 +287,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -266,22 +298,28 @@
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="100 ps" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="20000 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -290,7 +328,13 @@
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -304,6 +348,7 @@
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -314,17 +359,20 @@
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0x1FFF" xil_pn:valueState="non-default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behav" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
......@@ -346,6 +394,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<<<<<<< HEAD
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -452,11 +501,157 @@
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
=======
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>>>>>>> EG_sim
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<<<<<<< HEAD
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......@@ -737,6 +932,390 @@
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=======
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../sim/i2c_bus_model.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../sim/i2c_master_and_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../sim/testbench.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="127"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="127"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../sim/testbench_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../sim/print_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
>>>>>>> EG_sim
</file>
</files>
......
......@@ -303,7 +303,7 @@ begin
inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then
if (inhibit_cnt = 9) then --1999) then
inhibit_first_pulse <= '0';
end if;
end if;
......
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