Commit 771ca3df authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

WIP Merging with simulation branch

parents e18f593d 198e95b5
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C bus model
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-27
--
-- version: 1.0
--
-- description:
-- A very simple I2C bus model for use in simulation, implementing the
-- wired-AND on the I2C protocol.
--
-- Masters and slaves should implement the buffers internally and connect the
-- SCL and SDA lines to the input ports of this model, as below:
-- - masters should connect to mscl_i and msda_i
-- - slaves should connect to sscl_i and ssda_i
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-27 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end entity i2c_bus_model;
architecture behav of i2c_bus_model is
--==============================================================================
-- architecture begin
--==============================================================================
begin
scl_o <= '1' when (mscl_i = (mscl_i'range => '1')) and
(sscl_i = (sscl_i'range => '1')) else
'0';
sda_o <= '1' when (msda_i = (msda_i'range => '1')) and
(ssda_i = (ssda_i'range => '1')) else
'0';
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
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#
# Create work library
#
vlib work
#
# Compile sources
#
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/fastevent_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
vcom -explicit -93 "./print_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
vcom -explicit -93 "../top/conv_ttl_rs485.vhd"
vcom -explicit -93 "./testbench_pkg.vhd"
vcom -explicit -93 "./i2c_master_and_driver.vhd"
vcom -explicit -93 "./i2c_bus_model.vhd"
vcom -explicit -93 "./testbench.vhd"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ns -lib work work.testbench
#
# Source the wave do file
#
do {testbench_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {testbench.udo}
#
# Run simulation for this time
#
run 2 ms
#
# End
#
\ No newline at end of file
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...@@ -303,7 +303,7 @@ begin ...@@ -303,7 +303,7 @@ begin
inhibit_first_pulse <= '1'; inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1; inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then if (inhibit_cnt = 9) then --1999) then
inhibit_first_pulse <= '0'; inhibit_first_pulse <= '0';
end if; end if;
end if; end if;
......
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