Commit 9c4bd1d7 authored by Evangelia Gousiou's avatar Evangelia Gousiou

testbench: added counter of the number of pulses; added counter of the number of errors

parent a4a7ec2c
This diff is collapsed.
...@@ -47,9 +47,12 @@ package testbench_pkg is ...@@ -47,9 +47,12 @@ package testbench_pkg is
constant C_NR_MASTERS : positive := 1; constant C_NR_MASTERS : positive := 1;
constant C_NR_SLAVES : positive := 1; constant C_NR_SLAVES : positive := 1;
constant C_RTM : std_logic_vector(5 downto 0) := "010101";
constant C_INITIAL_TST_VALUE : std_logic_vector(31 downto 0) := x"FFFFFFF0";
-- DUT register map: -- DUT register map:
constant C_BIDR : std_logic_vector(31 downto 0) := x"00000000"; constant C_BIDR : std_logic_vector(31 downto 0) := x"00000000";
constant C_SR : std_logic_vector(31 downto 0) := x"00000004"; constant C_SR : std_logic_vector(31 downto 0) := x"00000004";
constant C_ERR : std_logic_vector(31 downto 0) := x"00000008"; constant C_ERR : std_logic_vector(31 downto 0) := x"00000008";
...@@ -129,7 +132,6 @@ package testbench_pkg is ...@@ -129,7 +132,6 @@ package testbench_pkg is
i2c_master_rcvd_val : std_logic_vector(31 downto 0); i2c_master_rcvd_val : std_logic_vector(31 downto 0);
end record; end record;
--============================================================================ --============================================================================
-- Components declarations -- Components declarations
--============================================================================ --============================================================================
...@@ -242,6 +244,8 @@ end component conv_ttl_rs485; ...@@ -242,6 +244,8 @@ end component conv_ttl_rs485;
procedure generate_pulse (signal pulse_n_out : out std_logic; procedure generate_pulse (signal pulse_n_out : out std_logic;
nb_of_pulses : in natural; nb_of_pulses : in natural;
fp_or_rp : in string (1 to 2);
signal rs485_fs_n : out std_logic;
ns_on : in time; ns_on : in time;
ns_off : in time); ns_off : in time);
...@@ -251,7 +255,29 @@ end component conv_ttl_rs485; ...@@ -251,7 +255,29 @@ end component conv_ttl_rs485;
signal sw_gp_n : out std_logic_vector(7 downto 0); signal sw_gp_n : out std_logic_vector(7 downto 0);
signal sw_other : out std_logic_vector(31 downto 0); signal sw_other : out std_logic_vector(31 downto 0);
signal pcbrev : out std_logic_vector(5 downto 0); signal pcbrev : out std_logic_vector(5 downto 0);
signal rtmm : out std_logic_vector(2 downto 0)); signal rtm : out std_logic_vector(5 downto 0));
procedure cnt_pulses (signal pulse_train : in std_logic;
signal nb_of_pulses_cnted : out natural;
nb_pulses_expected : in integer);
procedure write_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out : in t_i2c_master_out;
constant slv_addr : in std_logic_vector( 6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
constant send_val : in std_logic_vector(31 downto 0);
err : out natural);
procedure read_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out: in t_i2c_master_out;
constant slv_addr : in std_logic_vector(6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
signal rcvd_val : out std_logic_vector(31 downto 0);
constant exp_val : in std_logic_vector(31 downto 0);
err : out natural);
end testbench_pkg; end testbench_pkg;
package body testbench_pkg is package body testbench_pkg is
...@@ -263,7 +289,7 @@ package body testbench_pkg is ...@@ -263,7 +289,7 @@ package body testbench_pkg is
signal sw_gp_n : out std_logic_vector(7 downto 0); signal sw_gp_n : out std_logic_vector(7 downto 0);
signal sw_other : out std_logic_vector(31 downto 0); signal sw_other : out std_logic_vector(31 downto 0);
signal pcbrev : out std_logic_vector(5 downto 0); signal pcbrev : out std_logic_vector(5 downto 0);
signal rtmm : out std_logic_vector(2 downto 0)) is signal rtm : out std_logic_vector(5 downto 0)) is
begin begin
sw_gp_n(7) <= glitch_filter_en; sw_gp_n(7) <= glitch_filter_en;
if glitch_filter_en = '1' then if glitch_filter_en = '1' then
...@@ -279,34 +305,150 @@ package body testbench_pkg is ...@@ -279,34 +305,150 @@ package body testbench_pkg is
print_now("TTL output BAR disabled"); print_now("TTL output BAR disabled");
end if; end if;
print_now_s_std("RTMP & RTMM set to x", C_RTM);
sw_gp_n(6 downto 1) <= (others => '0'); -- not used sw_gp_n(6 downto 1) <= (others => '0'); -- not used
sw_other <= (others => '0'); -- not used sw_other <= (others => '0'); -- not used
pcbrev <= "111100"; -- not used pcbrev <= "111100"; -- not used
rtmm <= (others => '0'); -- not used rtm <= C_RTM; -- not used
end procedure; end procedure;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
procedure generate_pulse (signal pulse_n_out : out std_logic; procedure generate_pulse (signal pulse_n_out : out std_logic;
nb_of_pulses : in natural; nb_of_pulses : in natural;
ns_on : in time; fp_or_rp : in string (1 to 2);
ns_off : in time) is signal rs485_fs_n : out std_logic;
ns_on : in time;
ns_off : in time) is
variable numb_cnt : natural; variable numb_cnt : natural;
begin begin
numb_cnt := 0; numb_cnt := 0;
while not(numb_cnt = nb_of_pulses) loop while not(numb_cnt = nb_of_pulses) loop
pulse_n_out <= '1'; if fp_or_rp = "fp" then
wait for ns_off; rs485_fs_n <= '0'; -- stays inactive
pulse_n_out <= '0';
wait for ns_on; pulse_n_out <= '1';
pulse_n_out <= '1'; wait for ns_off;
pulse_n_out <= '0';
wait for ns_on;
pulse_n_out <= '1';
else
pulse_n_out <= '1';
rs485_fs_n <= '0';
wait for ns_off;
pulse_n_out <= '0';
rs485_fs_n <= '1';
wait for ns_on;
pulse_n_out <= '1';
rs485_fs_n <= '0';
end if;
numb_cnt:= numb_cnt + 1; numb_cnt:= numb_cnt + 1;
end loop; end loop;
wait for ns_off;
end procedure generate_pulse; end procedure generate_pulse;
----------------------------------------------------------------------------------------------------
procedure cnt_pulses (signal pulse_train : in std_logic;
signal nb_of_pulses_cnted : out integer;
nb_pulses_expected : in integer) is
variable pulse_cnt : integer :=0;
variable err_sum : integer:=0;
begin
if rising_edge(pulse_train) then
pulse_cnt := pulse_cnt +1;
end if;
nb_of_pulses_cnted <= pulse_cnt;
if pulse_cnt = nb_pulses_expected then
print_now_s_i("[OK] counted: ", pulse_cnt);
else
print_now_s_i("[ERR] counted: ", pulse_cnt);
end if;
end procedure cnt_pulses;
----------------------------------------------------------------------------------------------------
procedure read_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out: in t_i2c_master_out;
constant slv_addr : in std_logic_vector(6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
signal rcvd_val : out std_logic_vector(31 downto 0);
constant exp_val : in std_logic_vector(31 downto 0);
err : out natural) is
variable err_cnt : natural := 0;
begin
print_now("---------------");
print_now("read_i2c: start");
i2c_m_in.i2c_master_start <= '0';
i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
i2c_m_in.i2c_master_slv_addr <= "1011110";
i2c_m_in.i2c_master_reg_addr <= (others => '0');
i2c_m_in.i2c_master_send_val <= (others => '1');
wait for 1us;
i2c_m_in.i2c_master_slv_addr <= slv_addr;
i2c_m_in.i2c_master_reg_addr <= reg_addr;
i2c_m_in.i2c_master_start <= '1';
i2c_m_in.i2c_master_rdwr <= '1'; --0: write
wait for C_CLK_20_PER;
i2c_m_in.i2c_master_start <= '0';
wait until i2c_m_out.i2c_master_finish = '1';
rcvd_val <= i2c_m_out.i2c_master_rcvd_val;
print_now_s_std_s_std("I2C value read from 0x", reg_addr(7 downto 0),
" is 0x",i2c_m_out.i2c_master_rcvd_val);
wait until i2c_m_out.i2c_master_finish = '0';
print_now("read_i2c: completed");
if i2c_m_out.i2c_master_rcvd_val = exp_val then
print_now_s_s("[OK] Correct reading from reg ", reg_name, "; expected value matches read value");
else
print_now_s_std_s_std("[ERR]: Read value from " & reg_name & ": ", i2c_m_out.i2c_master_rcvd_val,
"; expected value: ",exp_val);
err_cnt := err_cnt +1;
end if;
err := err_cnt;
print_now("---------------");
end procedure read_i2c;
----------------------------------------------------------------------------------------------------
procedure write_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out : in t_i2c_master_out;
constant slv_addr : in std_logic_vector( 6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
constant reg_name : string(1 to 8);
constant send_val : in std_logic_vector(31 downto 0);
err : out natural) is
variable err_cnt : natural := 0;
begin
print_now("---------------");
print_now("write_i2c: start");
i2c_m_in.i2c_master_start <= '0';
i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
i2c_m_in.i2c_master_slv_addr <= "1011110";
i2c_m_in.i2c_master_reg_addr <= (others => '0');
i2c_m_in.i2c_master_send_val <= (others => '1');
wait for 1us;
i2c_m_in.i2c_master_slv_addr <= slv_addr;
i2c_m_in.i2c_master_reg_addr <= reg_addr;
i2c_m_in.i2c_master_send_val <= send_val;
i2c_m_in.i2c_master_start <= '1';
i2c_m_in.i2c_master_rdwr <= '0'; --0: write
wait for C_CLK_20_PER;
i2c_m_in.i2c_master_start <= '0';
wait until i2c_m_out.i2c_master_ready = '1';
print_now_s_std_s("write_i2C: Value ", send_val, " written to reg " & reg_name);
print_now("---------------");
err := 0;
end procedure write_i2c;
end; end;
......
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