Commit c1ebffb5 authored by Evangelia Gousiou's avatar Evangelia Gousiou

WIP test bench

parent fadf5f25
......@@ -617,6 +617,7 @@ PACKAGE BODY print_pkg IS
END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_now_s_std_s_std(s1: IN string; vec1: IN std_logic_vector;s2: IN string; vec2: IN std_logic_vector) IS
......
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......@@ -33,20 +33,84 @@ package testbench_pkg is
--============================================================================
-- Clock periods
constant c_clk_20_per : time := 50 ns;
constant c_clk_125_per : time := 8 ns;
constant c_reset_width : time := 200 ns;
constant C_CLK_20_PER : time := 50 ns;
constant C_CLK_125_PER : time := 8 ns;
constant C_RESET_WIDTH : time := 200 ns;
-- DUT configuration (generics):
constant c_nr_chans : integer := 6;
constant c_nr_inv_chans : integer := 4;
constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
constant c_gwvers : std_logic_vector(7 downto 0) :=x"40";
constant C_NR_CHANS : integer := 6;
constant C_NR_INV_CHANS : integer := 4;
constant C_BOARD_ID : std_logic_vector(31 downto 0) := x"54343835";
-- Number of I2C masters and slaves for the I2C bus model
constant c_nr_masters : positive := 1;
constant c_nr_slaves : positive := 1;
constant C_NR_MASTERS : positive := 1;
constant C_NR_SLAVES : positive := 1;
-- DUT register map:
constant C_BIDR : std_logic_vector(31 downto 0) := x"00000000";
constant C_SR : std_logic_vector(31 downto 0) := x"00000004";
constant C_ERR : std_logic_vector(31 downto 0) := x"00000008";
constant C_CR : std_logic_vector(31 downto 0) := x"0000000C";
constant C_CH1FPPCR : std_logic_vector(31 downto 0) := x"00000010";
constant C_CH2FPPCR : std_logic_vector(31 downto 0) := x"00000014";
constant C_CH3FPPCR : std_logic_vector(31 downto 0) := x"00000018";
constant C_CH4FPPCR : std_logic_vector(31 downto 0) := x"0000001C";
constant C_CH5FPPCR : std_logic_vector(31 downto 0) := x"00000020";
constant C_CH6FPPCR : std_logic_vector(31 downto 0) := x"00000024";
constant C_CH1RPPCR : std_logic_vector(31 downto 0) := x"00000028";
constant C_CH2RPPCR : std_logic_vector(31 downto 0) := x"0000002C";
constant C_CH3RPPCR : std_logic_vector(31 downto 0) := x"00000030";
constant C_CH4RPPCR : std_logic_vector(31 downto 0) := x"00000034";
constant C_CH5RPPCR : std_logic_vector(31 downto 0) := x"00000038";
constant C_CH6RPPCR : std_logic_vector(31 downto 0) := x"0000003C";
type t_reg is
record
reg_addr : std_logic_vector(31 downto 0);
reg_name : string(1 to 8);
end record;
type t_reg_table is array (natural range <>) of t_reg;
constant c_REG_MAP : t_reg_table(15 downto 0) :=
(0 => (reg_addr => C_BIDR,
reg_name => "BIDR "),
1 => (reg_addr => C_SR,
reg_name => "SR "),
2 => (reg_addr => C_ERR,
reg_name => "ERR "),
3 => (reg_addr => C_CR,
reg_name => "CR "),
4 => (reg_addr => C_CH1FPPCR,
reg_name => "CH1FPPCR"),
5 => (reg_addr => C_CH2FPPCR,
reg_name => "CH3FPPCR"),
6 => (reg_addr => C_CH3FPPCR,
reg_name => "CH3FPPCR"),
7 => (reg_addr => C_CH4FPPCR,
reg_name => "CH4FPPCR"),
8 => (reg_addr => C_CH5FPPCR,
reg_name => "CH5FPPCR"),
9 => (reg_addr => C_CH6FPPCR,
reg_name => "CH6FPPCR"),
10 => (reg_addr => C_CH1RPPCR,
reg_name => "CH1RPPCR"),
11 => (reg_addr => C_CH2RPPCR,
reg_name => "CH3RPPCR"),
12 => (reg_addr => C_CH3RPPCR,
reg_name => "CH3RPPCR"),
13 => (reg_addr => C_CH4RPPCR,
reg_name => "CH4RPPCR"),
14 => (reg_addr => C_CH5RPPCR,
reg_name => "CH5RPPCR"),
15 => (reg_addr => C_CH6RPPCR,
reg_name => "CH6RPPCR"));
--============================================================================
-- Types declarations
......@@ -176,7 +240,7 @@ end component conv_ttl_rs485;
-- signal rcvd_val : out std_logic_vector(31 downto 0));
procedure generate_pulses (signal pulses_n_out : out std_logic_vector (c_nr_chans-1 downto 0);
procedure generate_pulse (signal pulse_n_out : out std_logic;
nb_of_pulses : in natural;
ns_on : in time;
ns_off : in time);
......@@ -200,7 +264,7 @@ package body testbench_pkg is
end procedure;
----------------------------------------------------------------------------------------------------
procedure generate_pulses (signal pulses_n_out : out std_logic_vector (c_nr_chans-1 downto 0);
procedure generate_pulse (signal pulse_n_out : out std_logic;
nb_of_pulses : in natural;
ns_on : in time;
ns_off : in time) is
......@@ -209,14 +273,17 @@ package body testbench_pkg is
begin
numb_cnt := 0;
while not(numb_cnt = nb_of_pulses) loop
pulses_n_out <= (others => '1');
wait for ns_off; --min period is 240us??
pulses_n_out <= (others => '0');
pulse_n_out <= '1';
wait for ns_off;
pulse_n_out <= '0';
wait for ns_on;
pulses_n_out <= (others => '1');
pulse_n_out <= '1';
numb_cnt:= numb_cnt + 1;
end loop;
end procedure generate_pulses;
end procedure generate_pulse;
end;
......
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