Commit d4cad02b authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Modifies top file and conv-common and testbenches to allow for reset time to be…

Modifies top file and conv-common and testbenches to allow for reset time to be set as generic from top file and from testbench
parent 046a040f
...@@ -106,7 +106,8 @@ begin ...@@ -106,7 +106,8 @@ begin
-- Instantiate DUT -- Instantiate DUT
--============================================================================ --============================================================================
cmp_DUT: conv_ttl_rs485 cmp_DUT: conv_ttl_rs485
generic map (g_simul => false) generic map (g_simul => true,
g_rst_time => 10)
port map port map
( (
-- Clocks -- Clocks
......
...@@ -143,7 +143,9 @@ package testbench_pkg is ...@@ -143,7 +143,9 @@ package testbench_pkg is
-- Components declarations -- Components declarations
--============================================================================ --============================================================================
component conv_ttl_rs485 is component conv_ttl_rs485 is
generic (g_simul : boolean := FALSE); generic (g_simul : boolean := FALSE;
g_rst_time : positive := 10
);
port port
( (
-- Clocks -- Clocks
......
...@@ -49,7 +49,10 @@ use work.wishbone_pkg.all; ...@@ -49,7 +49,10 @@ use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all; use work.conv_common_gw_pkg.all;
entity conv_ttl_rs485 is entity conv_ttl_rs485 is
generic (g_simul : boolean := FALSE); generic (g_simul : boolean := false;
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_rst_time : positive := 2*(10**6)
);
port port
( (
-- Clocks -- Clocks
...@@ -345,6 +348,7 @@ begin ...@@ -345,6 +348,7 @@ begin
generic map generic map
( (
g_simul => g_simul, g_simul => g_simul,
g_rst_time => g_rst_time,
g_nr_chans => c_nr_chans, g_nr_chans => c_nr_chans,
g_board_id => c_board_id, g_board_id => c_board_id,
g_gwvers => c_gwvers, g_gwvers => c_gwvers,
......
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