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Conv TTL RS485 - Gateware
Commit e18f593d authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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WIP, changes for final release include re-organising channel i/o for db9 rtm

parent 4b63e998
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Showing with 197 additions and 149 deletions
conv-common-gw @ e65f9b5f
Subproject commit 28160cad7c141a3bfa1d9b90d3a80c911364a725 Subproject commit e65f9b5fe803086ff8f02f5dbc7bd1fa87f74cd3
syn/Release/conv_ttl_rs485.xise
View file @ e18f593d
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file> </file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/> <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="184"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="185"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="187"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="188"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="189"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="189"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file> </file>
</files> </files>
<bindings/> <bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/> <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project> </project>
top/conv_ttl_rs485.vhd
View file @ e18f593d
...@@ -166,7 +166,7 @@ architecture arch of conv_ttl_rs485 is ...@@ -166,7 +166,7 @@ architecture arch of conv_ttl_rs485 is
constant c_board_id : std_logic_vector(31 downto 0) := x"54343835"; constant c_board_id : std_logic_vector(31 downto 0) := x"54343835";
-- Gateware version -- Gateware version
constant c_gwvers : std_logic_vector(7 downto 0) := x"10"; constant c_gwvers : std_logic_vector(7 downto 0) := x"20";
--============================================================================ --============================================================================
-- Type declarations -- Type declarations
...@@ -188,6 +188,7 @@ architecture arch of conv_ttl_rs485 is ...@@ -188,6 +188,7 @@ architecture arch of conv_ttl_rs485 is
signal inv_pulse_out : std_logic_vector(c_nr_inv_chans-1 downto 0); signal inv_pulse_out : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal pulse_ttl : std_logic_vector(c_nr_chans-1 downto 0); signal pulse_ttl : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_rs485 : std_logic_vector(c_nr_chans-1 downto 0); signal pulse_rs485 : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_rs485_mapped : std_logic_vector(c_nr_chans-1 downto 0);
signal inhibit_first_pulse : std_logic; signal inhibit_first_pulse : std_logic;
signal inhibit_first_pulse_d0 : std_logic; signal inhibit_first_pulse_d0 : std_logic;
signal inhibit_cnt : unsigned(10 downto 0); signal inhibit_cnt : unsigned(10 downto 0);
...@@ -272,12 +273,21 @@ begin ...@@ -272,12 +273,21 @@ begin
pulse_ttl <= not ttl_n_i when sw_ttl = '1' else pulse_ttl <= not ttl_n_i when sw_ttl = '1' else
ttl_n_i and (not ttlbar_nosig); ttl_n_i and (not ttlbar_nosig);
-- Pulse input on RS-485 side valid only when failsafe not high -- Pulse input on RS-485 side valid only when failsafe not high
-- see Texas slyt257 for implementation details -- see Texas slyt257 for implementation details
gen_rs485_input : for i in 0 to c_nr_chans-1 generate gen_rs485_input : for i in 0 to c_nr_chans-1 generate
rs485_fs(i) <= rs485_n_i(i) nor rs485_fs_n_i(i); rs485_fs(i) <= rs485_n_i(i) nor rs485_fs_n_i(i);
pulse_rs485(i) <= (not rs485_n_i(i)) when rs485_fs(i) = '0' else '0'; pulse_rs485_mapped(i) <= (not rs485_n_i(i)) when rs485_fs(i) = '0' else '0';
pulse_rs485(0) <= pulse_rs485_mapped(0);
pulse_rs485(1) <= pulse_rs485_mapped(4) when rtmp_i = "101" else pulse_rs485_mapped(1);
pulse_rs485(2) <= pulse_rs485_mapped(2) when rtmp_i = "101" else pulse_rs485_mapped(2);
pulse_rs485(3) <= pulse_rs485_mapped(3) when rtmp_i = "101" else pulse_rs485_mapped(3);
pulse_rs485(4) <= pulse_rs485_mapped(1) when rtmp_i = "101" else pulse_rs485_mapped(4);
pulse_rs485(5) <= pulse_rs485_mapped(5) when rtmp_i = "101" else pulse_rs485_mapped(5);
end generate gen_rs485_input; end generate gen_rs485_input;
...@@ -335,7 +345,7 @@ begin ...@@ -335,7 +345,7 @@ begin
cmp_conv_common : conv_common_gw cmp_conv_common : conv_common_gw
generic map generic map
( (
-- Number of repeater channels
g_nr_chans => c_nr_chans, g_nr_chans => c_nr_chans,
g_board_id => c_board_id, g_board_id => c_board_id,
g_gwvers => c_gwvers, g_gwvers => c_gwvers,
...@@ -470,25 +480,35 @@ begin ...@@ -470,25 +480,35 @@ begin
bicolor_led_line_oen_o => bicolor_led_line_oen bicolor_led_line_oen_o => bicolor_led_line_oen
); );
--============================================================================
-- Channel output logic
--============================================================================
-- Front and rear panel outputs
ttl_o <= pulse_out when sw_ttl = '1' else ttl_o <= pulse_out when sw_ttl = '1' else
not pulse_out; not pulse_out;
rs485_o (1 downto 0) <= pulse_out (1 downto 0); -- rs485_o (1 downto 0) <= pulse_out (1 downto 0);
-- Channels 3 and 4 output copies of chans 1 and 2 respectively -- Channels 3 and 4 output copies of chans 1 and 2 respectively
-- depending on RTMP Id of RTM connected. -- depending on RTMP Id of RTM connected.
-- *RTM with DB9 connectors has only 2 o/p channels in rs485 RTMP = Gnd Open Gnd -- *RTM with DB9 connectors has only 2 o/p channels in rs485 RTMP = Gnd Open Gnd
-- *Optical RTM only 2 o/p channels in optical RTMP= Open Open Gnd -- *Optical RTM only 2 o/p channels in optical RTMP= Open Open Gnd
-- in these cases channel 3 copies channel 1 -- in these cases channel 3 copies channel 1
-- channel 4 copies channel 2 -- channel 4 copies channel 2
rs485_o (3 downto 2) <= pulse_out (1 downto 0) when rtmp_i = "101" or rtmp_i = "100"
else pulse_out (3 downto 2);
rs485_o (5 downto 4) <= pulse_out (5 downto 4);
-- rs485_o (3 downto 2) <= pulse_out (1 downto 0) when rtmp_i = "101" or rtmp_i = "100"
-- else pulse_out (3 downto 2);
-- rs485_o (5 downto 4) <= pulse_out (5 downto 4);
--============================================================================
-- Channel output logic
--============================================================================
-- Front and rear panel outputs
rs485_o(0) <= pulse_out(0);
rs485_o(1) <= pulse_out(0) when rtmp_i = "101" else pulse_out(1);
rs485_o(2) <= pulse_out(2);
rs485_o(3) <= pulse_out(3);
rs485_o(4) <= pulse_out(1) when rtmp_i = "101" else pulse_out(4);
rs485_o(5) <= pulse_out(1) when rtmp_i = "101" else pulse_out(5);
-- LED outputs -- LED outputs
-- Boards earlier than v4 do not use -ve logic for LEDs. -- Boards earlier than v4 do not use -ve logic for LEDs.
-- For these LED pulse signals are still in +ve logic. -- For these LED pulse signals are still in +ve logic.
......
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