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Conv TTL RS485 - Gateware
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Projects
Conv TTL RS485 - Gateware
Commits
f5df7ceb
Commit
f5df7ceb
authored
Jan 06, 2015
by
Theodor-Adrian Stana
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doc: Small changes and additions to HDL guide
parent
28b9e276
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364 deletions
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cern-title.tex
doc/hdlg/cern-title.tex
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conv-regs.tex
doc/hdlg/conv-regs.tex
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block-diagram.svg
doc/hdlg/fig/block-diagram.svg
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first-pulse-inhibit.svg
doc/hdlg/fig/first-pulse-inhibit.svg
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hdlg-conv-ttl-rs485.tex
doc/hdlg/hdlg-conv-ttl-rs485.tex
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doc/hdlg/cern-title.tex
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\noindent
\rule
{
\textwidth
}{
.1cm
}
\hfill
January
5
, 2015
\hfill
January
6
, 2015
\vspace*
{
3cm
}
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doc/hdlg/conv-regs.tex
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f5df7ceb
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\hline
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\\
\hline
\multicolumn
{
1
}{
|c|
}{
\cellcolor
{
gray!25
}
WRPRES
}
&
\multicolumn
{
1
}{
|c|
}{
\cellcolor
{
gray!25
}
I2C
\_
WDTO
}
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|c|
}{
\cellcolor
{
gray!25
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RTM[5:0]
}
\\
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-
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I2C
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WDTO
}
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\end{small}
\item
\begin{small}
{
\bf
WRPRES
}
[
\emph
{
read-only
}
]: White Rabbit present
\\
1 -- White Rabbit present
\\
0 -- White Rabbit not present
\end{small}
\item
\begin{small}
{
\bf
I2C
\_
ERR
}
[
\emph
{
read/write
}
]: I2C communication error
\\
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@@ -144,7 +137,8 @@ I2C\_ERR
\textbf
{
Unimplemented bits
}
: write as '0', read undefined
\end{small}
\end{itemize}
\vspace
{
11pt
}
\pagebreak
\subsubsection
{
CR -- Control Register
}
\label
{
app:conv-regs-cr
}
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doc/hdlg/fig/block-diagram.svg
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doc/hdlg/fig/first-pulse-inhibit.svg
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x=
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style=
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</tspan><tspan
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doc/hdlg/hdlg-conv-ttl-rs485.tex
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@@ -75,7 +75,7 @@ work, see \\
\multicolumn
{
1
}{
c
}{
\textbf
{
Date
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Version
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Change
}}
\\
\hline
06-08-2014
&
0.1
&
First draft
\\
0
5
-01-2015
&
0.2
&
Release for gateware v0.0
\\
0
6
-01-2015
&
0.2
&
Release for gateware v0.0
\\
\hline
\end{tabular}
}
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@@ -99,6 +99,7 @@ FPGA & Field-Programmable Gate Array \\
LSR
&
Line Status Register
\\
OSWR
&
Other Switches Register
\\
SR
&
Status Register
\\
SNMP
&
Simple Network Management Protocol
\\
\end{tabular}
\addcontentsline
{
toc
}{
section
}{
List of abbreviations
}
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@@ -112,7 +113,7 @@ SR & Status Register \\
This document is the HDL guide for the CONV-TTL-RS485 project~
\cite
{
conv-ttl-rs485-ohwr
}
.
The HDL for the CONV-TTL-RS485 board uses the converter board common gateware~
\cite
{
conv-common-gw
}
as a subproject and adds some external logic to it to adapt for peculiarities on the CONV-TTL-RS485.
This
short HDL guide
explains these peculiarities and the corresponding logic implemented, and lists
This
document
explains these peculiarities and the corresponding logic implemented, and lists
the memory map for the gateware in Appendix~
\ref
{
app:memmap
}
.
\subsection
{
Additional documentation
}
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