Commit fadf5f25 authored by Evangelia Gousiou's avatar Evangelia Gousiou

wip

parent 3afb5319
...@@ -134,6 +134,7 @@ PACKAGE print_pkg IS ...@@ -134,6 +134,7 @@ PACKAGE print_pkg IS
PROCEDURE print_now_s_dl (s: IN string; s2: IN std_logic_vector); PROCEDURE print_now_s_dl (s: IN string; s2: IN std_logic_vector);
PROCEDURE print_now_s_std (s: IN string; bit: IN std_logic); PROCEDURE print_now_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_now_s_std (s: IN string; vec: IN std_logic_vector); PROCEDURE print_now_s_std (s: IN string; vec: IN std_logic_vector);
PROCEDURE print_now_s_std_s_std (s1: IN string; vec1: IN std_logic_vector;s2: IN string; vec2: IN std_logic_vector);
FUNCTION char_to_std_logic_vector(arg : character) RETURN std_logic_vector; FUNCTION char_to_std_logic_vector(arg : character) RETURN std_logic_vector;
FUNCTION std_logic_vector_to_char(arg : std_logic_vector(7 DOWNTO 0)) RETURN character; FUNCTION std_logic_vector_to_char(arg : std_logic_vector(7 DOWNTO 0)) RETURN character;
...@@ -616,6 +617,21 @@ PACKAGE BODY print_pkg IS ...@@ -616,6 +617,21 @@ PACKAGE BODY print_pkg IS
END print_now_s_std; END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_now_s_std_s_std(s1: IN string; vec1: IN std_logic_vector;s2: IN string; vec2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s1);
HWRITE(l, vec1);
WRITE(l, s2);
HWRITE(l, vec2);
WRITELINE(output,l);
END print_now_s_std_s_std;
---------------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert character to std_logic_vector -- function to convert character to std_logic_vector
FUNCTION char_to_std_logic_vector( arg : character) RETURN std_logic_vector IS FUNCTION char_to_std_logic_vector( arg : character) RETURN std_logic_vector IS
......
...@@ -107,7 +107,7 @@ architecture behav of testbench is ...@@ -107,7 +107,7 @@ architecture behav of testbench is
signal sscl, ssda : std_logic_vector(c_nr_slaves-1 downto 0); signal sscl, ssda : std_logic_vector(c_nr_slaves-1 downto 0);
signal scl, sda : std_logic; signal scl, sda : std_logic;
--- ---
signal buf_byte_cnt: integer; signal buf_byte_cnt, nb_pulses_to_send : natural;
procedure read_i2c (signal i2c_m_in : out t_i2c_master_in; procedure read_i2c (signal i2c_m_in : out t_i2c_master_in;
...@@ -116,7 +116,7 @@ architecture behav of testbench is ...@@ -116,7 +116,7 @@ architecture behav of testbench is
constant reg_addr : in std_logic_vector(31 downto 0); constant reg_addr : in std_logic_vector(31 downto 0);
signal rcvd_val : out std_logic_vector(31 downto 0)) is signal rcvd_val : out std_logic_vector(31 downto 0)) is
begin begin
report "read_i2c: start "; print_now("read_i2c: start");
i2c_m_in.i2c_master_start <= '0'; i2c_m_in.i2c_master_start <= '0';
i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
...@@ -132,10 +132,11 @@ architecture behav of testbench is ...@@ -132,10 +132,11 @@ architecture behav of testbench is
i2c_m_in.i2c_master_start <= '0'; i2c_m_in.i2c_master_start <= '0';
wait until i2c_m_out.i2c_master_finish = '1'; wait until i2c_m_out.i2c_master_finish = '1';
rcvd_val <= i2c_m_out.i2c_master_rcvd_val; rcvd_val <= i2c_m_out.i2c_master_rcvd_val;
print_s_std("-------> I2C value read from ", reg_addr); print_now_s_std_s_std("-------> I2C value read from 0x", reg_addr(7 downto 0),
print_s_std("is: ", i2c_m_out.i2c_master_rcvd_val); " is 0x",i2c_m_out.i2c_master_rcvd_val);
wait until i2c_m_out.i2c_master_finish = '0'; wait until i2c_m_out.i2c_master_finish = '0';
report "read_i2c: OK "; print_now("read_i2c: completed");
end procedure read_i2c; end procedure read_i2c;
--============================================================================== --==============================================================================
...@@ -333,6 +334,7 @@ begin ...@@ -333,6 +334,7 @@ begin
--i2c access --i2c access
p_stim_i2c : process p_stim_i2c : process
begin begin
nb_pulses_to_send <= 250;
i2c_m_in.i2c_master_start <= '0'; i2c_m_in.i2c_master_start <= '0';
i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
i2c_m_in.i2c_master_slv_addr <= "1011110"; i2c_m_in.i2c_master_slv_addr <= "1011110";
...@@ -341,93 +343,21 @@ begin ...@@ -341,93 +343,21 @@ begin
wait until vme_sysreset_n = '1'; wait until vme_sysreset_n = '1';
report "started stimulus";
wait for 1us; wait for 6us; -- for resets and inhibit_pulse to have finished
generate_pulses (ttl_n_in, 250); print_now_s_i("Sending pulses: ", nb_pulses_to_send);
generate_pulses (ttl_n_in, nb_pulses_to_send, 100ns, 100ns);
read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0000", i2c_master_rcvd_val ); read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0000", i2c_master_rcvd_val );
read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0010", i2c_master_rcvd_val ); read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0010", i2c_master_rcvd_val );
read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0014", i2c_master_rcvd_val ); read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0014", i2c_master_rcvd_val );
read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0018", i2c_master_rcvd_val ); --11 difference read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0018", i2c_master_rcvd_val );
read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0000", i2c_master_rcvd_val ); --11 difference read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0000", i2c_master_rcvd_val );
end process p_stim_i2c; end process p_stim_i2c;
--i2c access
-- p_stim_i2c : process
-- begin
-- i2c_m_in.i2c_master_start <= '0';
-- i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
-- i2c_m_in.i2c_master_slv_addr <= "1011110";
-- i2c_m_in.i2c_master_reg_addr <= (others => '0');
-- i2c_m_in.i2c_master_send_val <= (others => '1');
-- wait until vme_sysreset_n = '1';
-- report "started stimulus";
-- wait for 50us;
-- settings_config (sw_gp_n_in, sw_other_in, pcbrev, rtmm_in);
-- generate_pulses (ttl_n_in, 2000);
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0000", i2c_master_rcvd_val1 );
-- end process p_stim_i2c;
-- i2c access
-- p_stim_i2c : process
-- begin
-- i2c_m_in.i2c_master_start <= '0';
-- i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
-- i2c_m_in.i2c_master_slv_addr <= "1011110"; -- I2C slave base address??
-- i2c_m_in.i2c_master_reg_addr <= (others => '0');
-- i2c_m_in.i2c_master_send_val <= (others => '1');
-- wait until vme_sysreset_n = '1';
-- report "started stimulus";
-- wait for 50us;
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0000", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0000" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_000C", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0000" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0034", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0000" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0038", i2c_master_rcvd_val );
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_002c", i2c_master_rcvd_val );
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_000C", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_000C" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0010", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0010" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0014", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0014" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0018", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0018" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- end process p_stim_i2c;
end architecture behav; end architecture behav;
--============================================================================== --==============================================================================
-- architecture end -- architecture end
......
...@@ -35,7 +35,7 @@ package testbench_pkg is ...@@ -35,7 +35,7 @@ package testbench_pkg is
-- Clock periods -- Clock periods
constant c_clk_20_per : time := 50 ns; constant c_clk_20_per : time := 50 ns;
constant c_clk_125_per : time := 8 ns; constant c_clk_125_per : time := 8 ns;
constant c_reset_width : time := 1 us; constant c_reset_width : time := 200 ns;
-- DUT configuration (generics): -- DUT configuration (generics):
...@@ -43,9 +43,8 @@ package testbench_pkg is ...@@ -43,9 +43,8 @@ package testbench_pkg is
constant c_nr_inv_chans : integer := 4; constant c_nr_inv_chans : integer := 4;
constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f"; constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
constant c_gwvers : std_logic_vector(7 downto 0) :=x"40"; constant c_gwvers : std_logic_vector(7 downto 0) :=x"40";
-- Number of I2C masters and slaves for the I2C bus model
-- Number of I2C masters and slaves for the I2C bus model
constant c_nr_masters : positive := 1; constant c_nr_masters : positive := 1;
constant c_nr_slaves : positive := 1; constant c_nr_slaves : positive := 1;
...@@ -177,87 +176,44 @@ end component conv_ttl_rs485; ...@@ -177,87 +176,44 @@ end component conv_ttl_rs485;
-- signal rcvd_val : out std_logic_vector(31 downto 0)); -- signal rcvd_val : out std_logic_vector(31 downto 0));
procedure generate_pulses (signal ttl_n_out: out std_logic_vector (c_nr_chans-1 downto 0); procedure generate_pulses (signal pulses_n_out : out std_logic_vector (c_nr_chans-1 downto 0);
numb : natural); nb_of_pulses : in natural;
ns_on : in time;
ns_off : in time);
end testbench_pkg; end testbench_pkg;
package body testbench_pkg is package body testbench_pkg is
--============================================================================== --==================================================================================================
-- Procedures -- Procedures
--============================================================================== --==================================================================================================
-- procedure write_i2c (signal slv_addr: in std_logic_vector( 6 downto 0);
-- signal reg_addr: in std_logic_vector(31 downto 0);
-- signal send_val: in std_logic_vector(31 downto 0)) is
-- begin
-- wait until i2c_master_ready = '1';
-- i2c_master_slv_addr <= slv_addr;
-- i2c_master_reg_addr <= reg_addr;
-- i2c_master_send_val <= send_val;
-- i2c_master_start <= '1';
-- i2c_master_rdwr <= '0'; --0: write
-- wait until i2c_master_ready = '1';
-- report "write_i2c: OK";
-- end procedure write_i2c;
procedure settings_config (signal sw_gp_n_in : out std_logic_vector(7 downto 0); procedure settings_config (signal sw_gp_n_in : out std_logic_vector(7 downto 0);
signal sw_other_in : out std_logic_vector(31 downto 0); signal sw_other_in : out std_logic_vector(31 downto 0);
signal pcbrev : out std_logic_vector(5 downto 0); signal pcbrev : out std_logic_vector(5 downto 0);
signal rtmm_in : out std_logic_vector(2 downto 0)) is signal rtmm_in : out std_logic_vector(2 downto 0)) is
begin begin
--wait for 2 us; -- does not work without this wait, no idea way ???
sw_gp_n_in(0) <= '1'; -- disable glitch filter ? sw_gp_n_in(0) <= '1'; -- disable glitch filter ?
sw_gp_n_in(1) <= '1'; sw_gp_n_in(1) <= '1'; --
sw_gp_n_in(7 downto 2) <= (others => '0'); sw_gp_n_in(7 downto 2) <= (others => '0');
sw_other_in <= (others => '0'); sw_other_in <= (others => '0');
pcbrev <= "111100"; pcbrev <= "111100";
rtmm_in <= (others => '0'); rtmm_in <= (others => '0');
end procedure; end procedure;
----------------------------------------------------------------------------------------------------
-- procedure read_i2c (signal i2c_m_out : in t_i2c_master_out; procedure generate_pulses (signal pulses_n_out : out std_logic_vector (c_nr_chans-1 downto 0);
-- signal i2c_m_in : out t_i2c_master_in; nb_of_pulses : in natural;
-- signal slv_addr : in std_logic_vector( 6 downto 0); ns_on : in time;
-- signal reg_addr : in std_logic_vector(31 downto 0); ns_off : in time) is
-- signal rcvd_val : out std_logic_vector(31 downto 0)) is
-- begin
-- report "read_i2c: start ";
-- i2c_m_in.i2c_master_start <= '0';
-- i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
-- i2c_m_in.i2c_master_slv_addr <= "1011110";
-- i2c_m_in.i2c_master_reg_addr <= (others => '0');
-- i2c_m_in.i2c_master_send_val <= (others => '1');
-- wait for 50us;
-- i2c_m_in.i2c_master_slv_addr <= slv_addr;
-- i2c_m_in.i2c_master_reg_addr <= reg_addr;
-- i2c_m_in.i2c_master_start <= '1';
-- i2c_m_in.i2c_master_rdwr <= '1'; --0: write
-- wait for c_clk_20_per;
-- i2c_m_in.i2c_master_start <= '0';
-- wait until i2c_m_out.i2c_master_finish = '1';
-- rcvd_val <= i2c_m_out.i2c_master_rcvd_val;
-- report "-------> I2C value read from x... " & integer'image(to_integer(unsigned(i2c_m_out.i2c_master_rcvd_val)));
-- report "read_i2c: OK ";
-- wait for 50us;
-- end procedure read_i2c;
procedure generate_pulses (signal ttl_n_out: out std_logic_vector (c_nr_chans-1 downto 0);
numb : natural) is
variable numb_cnt : natural; variable numb_cnt : natural;
begin begin
numb_cnt := 0; numb_cnt := 0;
while not(numb_cnt = numb) loop while not(numb_cnt = nb_of_pulses) loop
ttl_n_out <= (others => '1'); pulses_n_out <= (others => '1');
wait for 200 ns; --min period is 240us?? wait for ns_off; --min period is 240us??
ttl_n_out <= (others => '0'); pulses_n_out <= (others => '0');
wait for 100 ns; wait for ns_on;
ttl_n_out <= (others => '1'); pulses_n_out <= (others => '1');
wait for 200 ns; --min period is 240us??
numb_cnt:= numb_cnt + 1; numb_cnt:= numb_cnt + 1;
end loop; end loop;
end procedure generate_pulses; end procedure generate_pulses;
......
...@@ -293,7 +293,7 @@ begin ...@@ -293,7 +293,7 @@ begin
inhibit_first_pulse <= '1'; inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1; inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then if (inhibit_cnt = 9) then --1999) then
inhibit_first_pulse <= '0'; inhibit_first_pulse <= '0';
end if; end if;
end if; end if;
......
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