Conv TTL RS485 - Gateware:11f6c953a0878c3f1641bbad2c30f37d7532b890 commitshttps://ohwr.org/project/conv-ttl-rs485-gw/commits/11f6c953a0878c3f1641bbad2c30f37d7532b8902017-10-17T12:01:58Zhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/11f6c953a0878c3f1641bbad2c30f37d7532b890version of conv common-gw2017-10-17T12:01:58ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/6f27e6498770009cc8a65f36f8e46e6bf24c86d7Created sim folder2017-10-17T12:00:32ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/642847e4af7bc263d04d83026dbd22c384592314Created copies of chans 1 and 2 on chans 3 and 4 when opt and db9 rtms are used2017-10-16T08:26:27ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/42da5433a862de1add470db9d7d5c9b928433576Allocated 6 pcb version pins2017-10-12T15:07:56ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/5f14b08324269630f0467100aae981fca4724f7finv channel leds renamed2017-10-12T13:41:09ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/755d1fe05526ad2d65cf49e6d16a71771e9e7121front panel led pins renamed for -ve logic2017-10-12T13:39:50ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/78e79105a00343d6bcb70262773ed5520d291f22pulse leds set to +ve or -ve logic depending on the version of the board2017-10-12T11:46:19ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/c26346518a23c0e39f8e508d260e32e8c3087205fixed size of inv led vector2017-10-12T11:44:38ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/7c61ef819479c63293da35ce67605fb2cbea685aadded to the top entity the pcb version number coming from the pcb. connected…2017-10-10T10:15:15ZDenia Bouhireddenia.bouhired@cern.chadded to the top entity the pcb version number coming from the pcb. connected this to conv-common-gw for hwvers register
https://ohwr.org/project/conv-ttl-rs485-gw/commit/8aa6037cbe98ccb66cf927f42464e4ba009dc68eMoved inverter channel logic inside conv-common-gw. This includes inv-channel…2017-10-10T10:11:53ZDenia Bouhireddenia.bouhired@cern.chMoved inverter channel logic inside conv-common-gw. This includes inv-channel LEDs. Also now using negative logic for all LEDs
https://ohwr.org/project/conv-ttl-rs485-gw/commit/62d702839e5b1a1de369edcbbc16928edd9fe7ccSend front and rear pulse to conv-common-gw, not just the result of their OR…2017-10-10T09:54:52ZDenia Bouhireddenia.bouhired@cern.chSend front and rear pulse to conv-common-gw, not just the result of their OR operation. This is for implementing separate front and rear counters
https://ohwr.org/project/conv-ttl-rs485-gw/commit/e96b829782e6b6cf5bd52518bfb2a7456ea6b635added pulse width sel and burst_en inputs to conv-common entity2017-10-09T15:42:32ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/2df583b24415a52ac61457e08bad9c15aceccea5Corredct SFP port names, checked against schematics and ucf file2017-10-09T15:29:12ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/af664e7f27afea3c9aa27d8cfa43c2a661be3202Changed sfp port names in conv-common-gw new top entity2017-10-09T14:16:09ZDenia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/5f388feae52b22e6214842e2e29682a52c879dc8doc: Updated HDL guide to v1.12015-01-27T14:18:51ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/11bb728275984641589c55a94b5929bed972f05fdoc: Updated gateware test procedure to v0.22015-01-27T14:18:26ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/8c76fa81f1671bac2ae9687543a625df8f53b8fcdoc: Small correctional change in gateware test procedure2015-01-06T14:06:05ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/fa122aae6058dcfabb5953642dcfc9d91249ba53Updated top-level file for v1.0 release2015-01-06T13:45:40ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/4425d5cf9f18efd25c441cc5bec0c7e90464ae58doc: Updated HDL guide memory map and block diagram for v1.0 gateware2015-01-06T10:36:25ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/f5df7ceb175c411eef45ea9515733d0dcdd114d2doc: Small changes and additions to HDL guide2015-01-06T10:03:21ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/28b9e2760025eb95642c75777b2ab98825a70568Top-level file ready for golden v0.02015-01-05T17:17:38ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/72ab2f7e09848c0938e408f2765f837d085d7a23doc: Updated HDL guide for new v0.0 release2015-01-05T16:06:51ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/dade03a5e76154f47f70ae41b0cfeaa63f517196doc: Minor changes in gateware test procedure2015-01-05T16:06:25ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/669b9ba3ecbfad824e9b63009dc49ae66b3674adCompiled gateware for release version2014-12-18T16:51:21ZTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-rs485-gw/commit/3395277eea2a7be8eeda81a7a200dd6dfac73e4fReinitializing repository2014-12-18T12:28:05ZTheodor Stanat.stana@cern.ch