Commits · d373a166fab3fef31b28852c8b9d498825e5db34 · Projects / Conv TTL RS485

20 Sep, 2018 1 commit
- Created golden folder for synthesis and golden top file. Moved top release file to release folder · d373a166
  Denia Bouhired-Ferrag authored Sep 20, 2018
  
  d373a166
04 Jul, 2018 4 commits
- conv_common_gw submodule updated · 68406e40
  unknown authored Jul 04, 2018
  
  68406e40
- updated ise projects · 54d21202
  unknown authored Jul 04, 2018
  
  54d21202
- style changes only. vhdl checker run on file · bf4e34ef
  unknown authored Jul 04, 2018
  
  bf4e34ef
- top file modified to also reflect db9 rtm channel swaps on line status register… · c891396f
  unknown authored Jul 04, 2018
```
top file modified to also reflect db9 rtm channel swaps on line status register and on failsafe lines
```
  c891396f
12 Mar, 2018 5 commits
- updated conv-vommon-gw. g_rst_time in top entity and set from conv_ttl_rs485.vhd or from testbench · 3e79a0b0
  Denia Bouhired-Ferrag authored Mar 12, 2018
  
  3e79a0b0
- Modifies top file and conv-common and testbenches to allow for reset time to be… · d4cad02b
  Denia Bouhired-Ferrag authored Mar 12, 2018
```
Modifies top file and conv-common and testbenches to allow for reset time to be set as generic from top file and from testbench
```
  d4cad02b
- Updated ISE project to include testbench files · 046a040f
  Denia Bouhired-Ferrag authored Mar 12, 2018
  
  046a040f
- further merge of simulations with remote branch · 82bc89b2
  Denia Bouhired-Ferrag authored Mar 12, 2018
  
  82bc89b2
- WIP Merging with simulation branch · 771ca3df
  Denia Bouhired-Ferrag authored Mar 12, 2018
  
  771ca3df
09 Mar, 2018 2 commits
- added tests for the DB9 RTM; · ed12cb0e
  Evangelia Gousiou authored Mar 09, 2018
```
updated conv_ttl_rs485.vhd to the one from DB-new-conv-common-gw that treats the different RTMs
```
  ed12cb0e
- correction on glitch filter test; added two more tests of glitch filter with TTL bar · 289c8e93
  Evangelia Gousiou authored Mar 09, 2018
  
  289c8e93
06 Mar, 2018 1 commit
- WIP, changes for final release include re-organising channel i/o for db9 rtm · e18f593d
  Denia Bouhired-Ferrag authored Mar 06, 2018
  
  e18f593d
22 Feb, 2018 2 commits
- Updated version of conv-common-gw · 4b63e998
  Denia Bouhired-Ferrag authored Feb 22, 2018
  
  4b63e998
- DOC: wip unfinished modifications of gateware guide · 3173b753
  Denia Bouhired-Ferrag authored Feb 22, 2018
  
  3173b753
21 Feb, 2018 3 commits
- removed auto-gnerated-from-ise run.do · 198e95b5
  Evangelia Gousiou authored Feb 21, 2018
  
  198e95b5
- updated modelsim .do; updated .xise project to include simulation · 1e5e7608
  Evangelia Gousiou authored Feb 21, 2018
  
  1e5e7608
- added TTL bar test · 7d1e1f2c
  Evangelia Gousiou authored Feb 21, 2018
  
  7d1e1f2c
20 Feb, 2018 1 commit
- added glitch filter test · 8301a504
  Evangelia Gousiou authored Feb 20, 2018
  
  8301a504
19 Feb, 2018 1 commit
- added test for timetag reg and test for INV channels · 1351d6b2
  Evangelia Gousiou authored Feb 19, 2018
  
  1351d6b2
09 Feb, 2018 1 commit
- testbench: added counter of the number of pulses; added counter of the number of errors · 9c4bd1d7
  Evangelia Gousiou authored Feb 09, 2018
  
  9c4bd1d7
08 Feb, 2018 1 commit
- test bench added check for comparison of front and rear output; fixed rs485_fs input · a4a7ec2c
  Evangelia Gousiou authored Feb 08, 2018
  
  a4a7ec2c
07 Feb, 2018 1 commit
- WIP test bench · 03a4b568
  Evangelia Gousiou authored Feb 07, 2018
  
  03a4b568
06 Feb, 2018 1 commit
- WIP test bench · c1ebffb5
  Evangelia Gousiou authored Feb 06, 2018
  
  c1ebffb5
01 Feb, 2018 1 commit
- wip · fadf5f25
  Evangelia Gousiou authored Feb 01, 2018
  
  fadf5f25
31 Jan, 2018 2 commits
- wip; changed i2c prescaler to speed-up simulation · 3afb5319
  Evangelia Gousiou authored Jan 31, 2018
  
  3afb5319
- switched conv-common-gw branch to DB-rs485-integration · 954c8112
  Evangelia Gousiou authored Jan 31, 2018
```
testbench wip
```
  954c8112
30 Jan, 2018 1 commit
- WIP: testbench · 515449df
  Evangelia Gousiou authored Jan 30, 2018
  
  515449df
29 Jan, 2018 1 commit
- - switched conv-common-gw to the ML-sim branch · 32e5ada5
  Evangelia Gousiou authored Jan 29, 2018
```
- updated .xise to include simulation
```
  32e5ada5
17 Oct, 2017 3 commits
- style fixes, removed commented-out, old LED process · 4d40bcc3
  Denia Bouhired-Ferrag authored Oct 17, 2017
  
  4d40bcc3
- version of conv common-gw · 11f6c953
  Denia Bouhired-Ferrag authored Oct 17, 2017
  
  11f6c953
- Created sim folder · 6f27e649
  Denia Bouhired-Ferrag authored Oct 17, 2017
  
  6f27e649
16 Oct, 2017 1 commit
- Created copies of chans 1 and 2 on chans 3 and 4 when opt and db9 rtms are used · 642847e4
  Denia Bouhired-Ferrag authored Oct 16, 2017
  
  642847e4
12 Oct, 2017 5 commits
- Allocated 6 pcb version pins · 42da5433
  Denia Bouhired-Ferrag authored Oct 12, 2017
  
  42da5433
- inv channel leds renamed · 5f14b083
  Denia Bouhired-Ferrag authored Oct 12, 2017
  
  5f14b083
- front panel led pins renamed for -ve logic · 755d1fe0
  Denia Bouhired-Ferrag authored Oct 12, 2017
  
  755d1fe0
- pulse leds set to +ve or -ve logic depending on the version of the board · 78e79105
  Denia Bouhired-Ferrag authored Oct 12, 2017
  
  78e79105
- fixed size of inv led vector · c2634651
  Denia Bouhired-Ferrag authored Oct 12, 2017
  
  c2634651
10 Oct, 2017 2 commits
- added to the top entity the pcb version number coming from the pcb. connected… · 7c61ef81
  Denia Bouhired-Ferrag authored Oct 10, 2017
```
added to the top entity the pcb version number coming from the pcb. connected this to conv-common-gw for hwvers register
```
  7c61ef81
- Moved inverter channel logic inside conv-common-gw. This includes inv-channel… · 8aa6037c
  Denia Bouhired-Ferrag authored Oct 10, 2017
```
Moved inverter channel logic inside conv-common-gw. This includes inv-channel LEDs. Also now using negative logic for all LEDs
```
  8aa6037c