Conv-ttl-rs485 hardware review

Present:
=========
- Dimitris Lampridis
- Eva Gousiou
- Tristan Gingold
- Denia Bouhired

- Additional comments, post-review,from Erik Van der Bij

General:
=========
    DL: When opened on newer Altium (17), some labels are upside down 
    Action: In newer versions of Altium, go to DXP menue select Preferences>Schematic>Graphical Editing
    Uncheck "Display strings as rotated". This box is somehow checked on new versions of Altium.
    

    DL: 4k7 pull up resistors are used throughout. These may be too strong (10k would be enough)
    Action: DONE. Most of the resistors have been changed to 10k.
    
    DL: Manually added wire junctions (in red) on schematics, in places where it is not needed. 
    Action: DONE

CONV-TTL-RS485 motherboard
===========================

    DL: Sheet 2: why use B prefix for test points. Why not TP?
    Action: The actual schematic components are called "Black bead PCB ..." see BOM. 
    
    DL: Sheet 3, FPGA bank - tidy up and align ports
    Action: DONE
    
    DL: Sheet 3, Suggestion: Share pads for pull-up and pull-down resistors in 
    hw version number, in order to make sure only one is soldered
    Action: YES. This will be discussed with DEM for the best way for this to be implemented during layout
    
    DL: Sheet 5 VME P1 connector uses thicker loop back jumper-like wired. Why not a normal wire
    Action: DONE. A priori no reason for this. They have now been replaced by regular thickness wires.
    
    DL: Sheet 7, 9 Use hierarchical design and multichannel for front ttl: less error prone, 
    good for scalability.
    Sheet 9 Use multi channel, put buffers inside channel/investigate how to handle power of the buffer.
    Action: As far as I understand, to handle the multi-channel design, I have to
    use buses (to connect separate channels).This would involve having net and 
    port names that end with a numeral. In this case net names have channel numbers
    in the middle of the name, not on the end (Eg: RS485_RX_1_P or RS485_RX_1_P).
    It is concluded therefore that the operation would take a lot of signal relabeling
    on multiple sheets, which could outweight the benefits of adding the multi-channel feature.
    
    DL: Sheet 7 Different GND symbols used, try to unify
    Action: DONE
    
    DL: Investigate working with hidden pins for power symbols, for e.g. in sn74lvc14ad buffers. 
    Action: This is indeed possible. The connection to the power rail is set up
    in a dialogue box. I am not sure however this is very useful for this schematic. 
    The power pins are not that cumbersome. Keeping them connected explicitly will avoid 
    (review) questions and suspicion of human error.
    
    DL: Sheet 7 use NO ERC for unconnected pins in IC9
    Action: DONE

    DL: Are LED inverters the only way to resolve checking for power up phase. 
    Check if they are pulled down, or whether buffers do the job buffers output high.
    Actions:It seems like these I/O pins will be floating during configuration. 
    The inverting schmidt trigger data sheet specifies that floating inputs should 
    be tied to a level. Will add pull-down resistors for LEDs. DONE. 
    EG: Check masterfip led pullup design, check whether currents are similar on both LED types
    Action: This would make the circuit considerably simpler and would use the fewer components.
    However, it has been decided to keep the same circuit as used on the conv-ttl-blo board.
    
    DL: Sheet 8 Bicolor led current too high with 50ohm resistors, if LEDs are driven for too long.
       Actions: The current circuit and vhdl core are being used successfully on SVEC, conv-ttl-blo
                and conv-ttl-rs485 (prototype). There is no guarantee that the circuit 
                would work with a different core, nore should this possibility be built-in to the design. 
                A yellow note was added on the schematics as a disclaimer.
                
    EG: Sheet 8 Boxes surrounding bicolor LEDs are dashed red lines like "Not Mounted" boxes.
        Could be misleading.
    Action: DONE. Colour has been changed
    
    DL: Sheet 7: Move ESD strips to power supply sheet
    Move Fiduciaries to top level  
    Actions: Makes sense. DONE.
    
    EG: Sheet 9 ohwr licence partly hidden. Enlarge box.
    Action: DONE

    DL: Sheet 10, mirror schematics so that signal flow is from left to right. 
    Action: DONE

RTM in DB9 
===========
    EV: Numeral suffixes for output ports, rather than alphabetical (Eg: OUT_N_2_P instead of OUT_N_B_P)
    Action: DONE
    
    DL : Sheet 2 Remove Manual junction 
    Action: DONE
    
    DL: Sheet 3 use hierarchical design
    Action: DONE
    
    EG : Sheet 1 Top level sheet doesn’t have the word "top" 
    Action: DONE
    
    EG : Sheet 3 OHL licence present twice in last sheet
    Action: DONE 
    
    EG: In Wiki db9 mockup name output ports A, B, C, D, E
    Action: DONE (now 1,2,3,4,5)