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-- Title          : Wishbone slave core for PTS control and status registers
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-- File           : pts_regs.vhd
-- Author         : auto-generated by wbgen2 from pts_regs.wb
-- Created        : Thu Dec  4 10:03:35 2014
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pts_regs is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(1 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
    pts_bidr_i                               : in     std_logic_vector(31 downto 0);
-- Port for BIT field: 'Channel pulse LED enable' in reg: 'CSR'
    pts_csr_chledt_o                         : out    std_logic;
-- Port for BIT field: 'Status LED enable' in reg: 'CSR'
    pts_csr_stledt_o                         : out    std_logic;
-- Port for BIT field: 'Rear pulse LED line' in reg: 'CSR'
    pts_csr_rledt_o                          : out    std_logic;
-- Port for BIT field: 'TTL test enable' in reg: 'CSR'
    pts_csr_ttlpt_o                          : out    std_logic;
-- Port for BIT field: 'Rear pulse enable' in reg: 'CSR'
    pts_csr_rearpt_o                         : out    std_logic;
-- Port for BIT field: 'RS485 tester card VCC' in reg: 'CSR'
    pts_csr_tstcvcc_o                        : out    std_logic;
-- Port for BIT field: 'RS485 tester card MUX enable' in reg: 'CSR'
    pts_csr_tstcmuxen_o                      : out    std_logic;
-- Port for BIT field: 'RS485 tester card MUX S0 line' in reg: 'CSR'
    pts_csr_tstcs0_o                         : out    std_logic;
-- Port for BIT field: 'RS485 tester card MUX S1 line' in reg: 'CSR'
    pts_csr_tstcs1_o                         : out    std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
    pts_csr_rst_unlock_o                     : out    std_logic;
    pts_csr_rst_unlock_i                     : in     std_logic;
    pts_csr_rst_unlock_load_o                : out    std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CSR'
    pts_csr_rst_o                            : out    std_logic;
    pts_csr_rst_i                            : in     std_logic;
    pts_csr_rst_load_o                       : out    std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
    pts_csr_switch_i                         : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'CSR'
    pts_csr_rtm_i                            : in     std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
    pts_csr_i2c_err_o                        : out    std_logic;
    pts_csr_i2c_err_i                        : in     std_logic;
    pts_csr_i2c_err_load_o                   : out    std_logic;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'CSR'
    pts_csr_i2c_wdto_o                       : out    std_logic;
    pts_csr_i2c_wdto_i                       : in     std_logic;
    pts_csr_i2c_wdto_load_o                  : out    std_logic;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
    pts_lsr_front_i                          : in     std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
    pts_lsr_frontinv_i                       : in     std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
    pts_lsr_rear_i                           : in     std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
    pts_lsr_frontfs_i                        : in     std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
    pts_lsr_frontinvfs_i                     : in     std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
    pts_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Input termination enable' in reg: 'TER'
    pts_ter_iterm_o                          : out    std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER'
    pts_ter_oterm_o                          : out    std_logic_vector(5 downto 0)
  );
end pts_regs;

architecture syn of pts_regs is

signal pts_csr_chledt_int                       : std_logic      ;
signal pts_csr_stledt_int                       : std_logic      ;
signal pts_csr_rledt_int                        : std_logic      ;
signal pts_csr_ttlpt_int                        : std_logic      ;
signal pts_csr_rearpt_int                       : std_logic      ;
signal pts_csr_tstcvcc_int                      : std_logic      ;
signal pts_csr_tstcmuxen_int                    : std_logic      ;
signal pts_csr_tstcs0_int                       : std_logic      ;
signal pts_csr_tstcs1_int                       : std_logic      ;
signal pts_ter_iterm_int                        : std_logic_vector(5 downto 0);
signal pts_ter_oterm_int                        : std_logic_vector(5 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(1 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      pts_csr_chledt_int <= '0';
      pts_csr_stledt_int <= '0';
      pts_csr_rledt_int <= '0';
      pts_csr_ttlpt_int <= '0';
      pts_csr_rearpt_int <= '0';
      pts_csr_tstcvcc_int <= '0';
      pts_csr_tstcmuxen_int <= '0';
      pts_csr_tstcs0_int <= '0';
      pts_csr_tstcs1_int <= '0';
      pts_csr_rst_unlock_load_o <= '0';
      pts_csr_rst_load_o <= '0';
      pts_csr_i2c_err_load_o <= '0';
      pts_csr_i2c_wdto_load_o <= '0';
      pts_ter_iterm_int <= "000000";
      pts_ter_oterm_int <= "000000";
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          pts_csr_rst_unlock_load_o <= '0';
          pts_csr_rst_load_o <= '0';
          pts_csr_i2c_err_load_o <= '0';
          pts_csr_i2c_wdto_load_o <= '0';
          ack_in_progress <= '0';
        else
          pts_csr_rst_unlock_load_o <= '0';
          pts_csr_rst_load_o <= '0';
          pts_csr_i2c_err_load_o <= '0';
          pts_csr_i2c_wdto_load_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(1 downto 0) is
          when "00" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= pts_bidr_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01" => 
            if (wb_we_i = '1') then
              pts_csr_chledt_int <= wrdata_reg(0);
              pts_csr_stledt_int <= wrdata_reg(1);
              pts_csr_rledt_int <= wrdata_reg(2);
              pts_csr_ttlpt_int <= wrdata_reg(3);
              pts_csr_rearpt_int <= wrdata_reg(4);
              pts_csr_tstcvcc_int <= wrdata_reg(5);
              pts_csr_tstcmuxen_int <= wrdata_reg(6);
              pts_csr_tstcs0_int <= wrdata_reg(7);
              pts_csr_tstcs1_int <= wrdata_reg(8);
              pts_csr_rst_unlock_load_o <= '1';
              pts_csr_rst_load_o <= '1';
              pts_csr_i2c_err_load_o <= '1';
              pts_csr_i2c_wdto_load_o <= '1';
            end if;
            rddata_reg(0) <= pts_csr_chledt_int;
            rddata_reg(1) <= pts_csr_stledt_int;
            rddata_reg(2) <= pts_csr_rledt_int;
            rddata_reg(3) <= pts_csr_ttlpt_int;
            rddata_reg(4) <= pts_csr_rearpt_int;
            rddata_reg(5) <= pts_csr_tstcvcc_int;
            rddata_reg(6) <= pts_csr_tstcmuxen_int;
            rddata_reg(7) <= pts_csr_tstcs0_int;
            rddata_reg(8) <= pts_csr_tstcs1_int;
            rddata_reg(14) <= pts_csr_rst_unlock_i;
            rddata_reg(15) <= pts_csr_rst_i;
            rddata_reg(23 downto 16) <= pts_csr_switch_i;
            rddata_reg(29 downto 24) <= pts_csr_rtm_i;
            rddata_reg(30) <= pts_csr_i2c_err_i;
            rddata_reg(31) <= pts_csr_i2c_wdto_i;
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(5 downto 0) <= pts_lsr_front_i;
            rddata_reg(9 downto 6) <= pts_lsr_frontinv_i;
            rddata_reg(15 downto 10) <= pts_lsr_rear_i;
            rddata_reg(21 downto 16) <= pts_lsr_frontfs_i;
            rddata_reg(25 downto 22) <= pts_lsr_frontinvfs_i;
            rddata_reg(31 downto 26) <= pts_lsr_rearfs_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11" => 
            if (wb_we_i = '1') then
              pts_ter_iterm_int <= wrdata_reg(5 downto 0);
              pts_ter_oterm_int <= wrdata_reg(11 downto 6);
            end if;
            rddata_reg(5 downto 0) <= pts_ter_iterm_int;
            rddata_reg(11 downto 6) <= pts_ter_oterm_int;
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- ID register bits
-- Channel pulse LED enable
  pts_csr_chledt_o <= pts_csr_chledt_int;
-- Status LED enable
  pts_csr_stledt_o <= pts_csr_stledt_int;
-- Rear pulse LED line
  pts_csr_rledt_o <= pts_csr_rledt_int;
-- TTL test enable
  pts_csr_ttlpt_o <= pts_csr_ttlpt_int;
-- Rear pulse enable
  pts_csr_rearpt_o <= pts_csr_rearpt_int;
-- RS485 tester card VCC
  pts_csr_tstcvcc_o <= pts_csr_tstcvcc_int;
-- RS485 tester card MUX enable
  pts_csr_tstcmuxen_o <= pts_csr_tstcmuxen_int;
-- RS485 tester card MUX S0 line
  pts_csr_tstcs0_o <= pts_csr_tstcs0_int;
-- RS485 tester card MUX S1 line
  pts_csr_tstcs1_o <= pts_csr_tstcs1_int;
-- Reset unlock bit
  pts_csr_rst_unlock_o <= wrdata_reg(14);
-- Reset bit
  pts_csr_rst_o <= wrdata_reg(15);
-- switches
-- RTM
-- I2C communication error
  pts_csr_i2c_err_o <= wrdata_reg(30);
-- I2C communication watchdog timeout error
  pts_csr_i2c_wdto_o <= wrdata_reg(31);
-- Front panel channel input state
-- Front panel INV-TTL input state
-- Rear panel input state
-- Front panel input failsafe state
-- Front panel inverter input failsafe state
-- Rear panel input failsafe state
-- Input termination enable
  pts_ter_iterm_o <= pts_ter_iterm_int;
-- Output termination enable
  pts_ter_oterm_o <= pts_ter_oterm_int;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
